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Z8F082ASH020SC 参数 Datasheet PDF下载

Z8F082ASH020SC图片预览
型号: Z8F082ASH020SC
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采XP -R F08xA系列与扩展外设 [Z8 Encore XP-R F08xA Series with eXtended Peripherals]
分类和应用: 微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 244 页 / 2750 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8 Encore! XP® F08xA Series  
Product Specification  
56  
C1ENH—Port C1 Interrupt Request Enable High Bit  
C0ENH—Port C0 Interrupt Request Enable High Bit  
Table 43. IRQ2 Enable Low Bit Register (IRQ2ENL)  
BITS  
7
6
5
4
3
2
1
0
Reserved  
C3ENL  
0
C2ENL  
0
C1ENL  
0
C0ENL  
0
FIELD  
RESET  
R/W  
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
FC8H  
ADDR  
Reserved—Must be 0.  
C3ENL—Port C3 Interrupt Request Enable Low Bit  
C2ENL—Port C2 Interrupt Request Enable Low Bit  
C1ENL—Port C1 Interrupt Request Enable Low Bit  
C0ENL—Port C0 Interrupt Request Enable Low Bit  
Interrupt Edge Select Register  
The Interrupt Edge Select (IRQES) register (Table 44) determines whether an interrupt is  
generated for the rising edge or falling edge on the selected GPIO Port A or Port D input  
pin.  
Table 44. Interrupt Edge Select Register (IRQES)  
BITS  
7
6
5
4
3
2
1
0
IES7  
IES6  
IES5  
IES4  
IES3  
IES2  
IES1  
IES0  
FIELD  
RESET  
R/W  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
FCDH  
ADDR  
IESx—Interrupt Edge Select x  
0 = An interrupt request is generated on the falling edge of the PAx input or PDx.  
1 = An interrupt request is generated on the rising edge of the PAx input PDx.  
where x indicates the specific GPIO Port pin number (0 through 7).  
Shared Interrupt Select Register  
The Shared Interrupt Select (IRQSS) register (Table 45) determines the source of the  
PADxS interrupts. The Shared Interrupt Select register (Table 45) selects between Port A  
and alternate sources for the individual interrupts.  
PS024705-0405  
P R E L I M I N A R Y  
Interrupt Controller