Z86E30/E31/E40
Z8 4K OTP Microcontroller
Zilog
Expanded Register File (ERF). The register file has been
expanded to allow for additional system control registers,
mapping of additional peripheral devices and input/output
ports into the register address area. The Z8 register ad-
dress space R0 through R15 is implemented as 16 groups
of 16 registers per group (Figure 26). These register
groups are known as the Expanded Register File (ERF).
Register File. The register file consists of three I/O port
registers, 236/125 general-purpose registers, 15 control
and status registers, and three system configuration regis-
ters in the expanded register group. The instructions can
access registers directly or indirectly through an 8-bit ad-
dress field. This allows a short 4-bit register address using
the Register Pointer (Figure 24). In the 4-bit mode, the reg-
ister file is divided into 16 working register groups, each
occupying 16 continuous locations. The Register Pointer
addresses the starting location of the active working-regis-
ter group.
The low nibble (D3-D0) of the Register Pointer (RP) select
the active ERF group, and the high nibble (D7-D4) of reg-
ister RP select the working register group. Three system
configuration registers reside in the Expanded Register
File at bank FH: PCON, SMR, and WDTMR. The rest of
the Expanded Register is not physically implemented and
is reserved for future expansion.
Note: Register Bank E0-EF can only be accessed through
working register and indirect addressing modes. (This
bank is available in Z86E30/E40 only.)
R253 RP
D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register Group
Working Register Group
Default setting after RESET = 00000000
Figure 24. Register Pointer Register
34
P R E L I M I N A R Y
DS97Z8X0500
ZILOG [ ZILOG, INC. ]
