Z8018x Family
MPU User Manual
310
DMA TEND0 output 108
SLEEP 35
E clock (memory and I/O R/W cycles)201
E clock (R/W and INTACK cycles) 167
E clock (SLEEP and SYSTEM STOP
modes) 168
TRAP timing - 2nd Op Code Undefined71
TRAP timing - 3rd Op Code Undefined72
WAIT 28
E clock BUS RELEASE, SLEEP and SYS-
TEM STOP modes) 201
TRAP 68
E clock minimum timing example of
PWEL and PWEH) 202
External clock rise and fall 204
HALT 33
I/O Read and Write cycles with IOC = 017
I/O read and write cycles with IOC=117
I/O read/write timing 23
Input rise and fall time 204
Instruction 24
Interrupt 70
Timing 71
U
Undefined Fetch Object (UFO) 68
V
INT0 interrupt mode 2 80
INT0 mode 0 76
INT0 mode 1 78
INT1, INT2 and Internal interrupts 86
M1 temporary enable 16
Memory read/write timing (with Wait
state) 22
Vector acquisition
INT0 mode 2 79
INT1, INT2 81
Vector table 82
Memory read/write timing (without Wait
state) 21
W
Wait state generation
NMI and DMA operation 115
Op Code Fetch timing (with Wait state) 20
Op Code Fetch timing (without Wait state)
I/O Wait insertion 29
Memory and 29
19
PRT bus release mode 167
Refresh cycle 87
RESET 25
Programmable Wait state insertion28
Wait input and reset 30
RTS0 140
Wait state insertion 30
UM005001-ZMP0400
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