Z8018x Family
MPU User Manual
308
Memory and I/O Wait state insertion 29
Memory management unit (MMU) 13
Memory to ASCI 109
P
Pin description
A0 through CTS1 7
BUSREQ through RFSH 9
D0 through INT2 8
RTS0 through TEND1 10
TEST through XTAL 10
Memory to memory 105
MMU Register description 60
Mode
HALT 31
Pin package
IOSTOP 35
SLEEP 33
SYSTEM STOP 35
64-pin DIP 3
68-pin PLCC 4
80-pin QFP 5
Modem control signals 138
Programmable reload timer (PRT)14
N
Programming
Level-sense 109
NMI
and DMA operation timing diagram115
Use 74
PRT
Block diagram 157
Bus release mode timing diagram167
Interrupt request generation164
Timer control register 161
Non-maskable interrupt72
O
On-chip clock generator
R
Circuit board design rules170
External clock interface 169
Operating frequencies168
Refresh 87
Control register 88
Register
Operation modes
Control register 84
CPU timing 18
IOC 16
ASCI Control A0 125
ASCI Control A1 128
ASCI Control B 131
ASCI Status 0 120
ASCI Status 1 123
M1 Enable 15
M1 temporary enable 16
UM005001-ZMP0400
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