Z8018x Family
MPU User Manual
148
Bit
Position Bit/Field R/W
Value Description
End Flag — EF is set to 1 by the CSI/O to indicate
7
EF
R
completion of an 8-bit data transmit or receive operation.
If EIE (End Interrupt Enable) bit = 1 when EF is set to 1, a
CPU interrupt request is generated. Program access of
TRDR only occurs if EF is 1. The CSI/O clears EF to 0
when TRDR is read or written. EF is cleared to 0 during
RESET and IOSTOP mode.
6
5
EIE
RE
R/W
R/W
End Interrupt Enable — EIE is set to 1 to enable EF = 1
to generate a CPU interrupt request. The interrupt request
is inhibited if EIE is reset to 0. EIE is cleared to 0 during
RESET.
Receive Enable — A CSI/O receive operation is started
by setting RE to 1. When RE is set to 1, the data clock is
enabled. In internal clock mode, the data clock is output
from the CKS pin. In external dock mode, the dock is
input on the CKS pin. In either case, data is shifted in on
the RXS pin in synchronization with the (internal or
external) data clock. After receiving 8 bits of data, the
CSI/O automatically clears RE to 0, EF is set to 1, and an
interrupt (if enabled by EIE = 1) is generated. RE and TE
are never both set to 1 at the same time. RE is cleared to 0
during RESET and ISTOP mode.
RXS is multiplexed with CTS1 modem control input of
ASCI channel 1. In order to enable the RXS function, the
CTS1E bit in CNTA1 must be reset to 0.
UM005001-ZMP0400
ZILOG [ ZILOG, INC. ]
