Z8018x Family
MPU User Manual
145
2^ss depends on the three least significant bits of the CNTLB register, as
described in Table 21.
Table 21. 2^ss Values
ss2 ss1 ss0 2^ss
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
16
32
64
External Clock from CKA0
The ASCIs require a 50% duty cycle when CKA is used as an input.
Minimum High and Low times on CKA0 are typical of most CMOS
devices.
RDRF is set, and if enabled, an Rx Interrupt or DMA REquest is
generated when the receiver transfers a character from the Rx Shift
Register to the RX FIFO. The FIFO provides a margin against overruns.
When the is more than one character in the FIFO, and software or a DMA
channel reads a character, RDRF either remains set or is cleared and then
immediately set again. For example, if a receive interrupt service routine
does not real all the characters in the RxFIFO, RDRF and the interrupt
request remain asserted.
The Rx DMA request is disabled when any of the error flags PE or FE or
OVRN are set, so that software can identify with which character the
problem is associated.
If Bit 7, RDRF Interrupt Inhibit, is set to 1, the ASCI does not request a
Receive interrupt when its RDRF flag is 1. Set this bit when programming
a DMA channel to handle the receive data from an ASCI. The other
UM005001-ZMP0400
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