Z8018x Family
MPU User Manual
150
CSI/O Transmit/Receive Register (TRDR: 0BH)
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
CSI/O Transmit/Receive Data
R/W
0
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Table 22. CSI/O Baud Rate Selection
SS2
SS1
SS0
Divide Ratio
Baud Rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
¸ 20
(200000)
(100000)
(50000)
(25000)
(12500)
(6250)
¸ 40
¸ 80
¸ 160
¸ 320
¸ 640
¸ 1280
(3125)
External Clock input (less than ¸ 20)
Note: ( ) indicates the baud rate (BPS) at Phi = 4 MHz.
After RESET, the CKS pin is configured as an external clock input (SS2,
SS1, SS0 = 1). Changing these values causes CKS to become an output pin
and the selected clock is output when transmit or receive operations are
enabled.
CSI/O Interrupts
The CSI/O interrupt request circuit is shown in Figure 58.
UM005001-ZMP0400
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