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Z8018008VSC 参数 Datasheet PDF下载

Z8018008VSC图片预览
型号: Z8018008VSC
PDF下载: 下载PDF文件 查看货源
内容描述: 家庭MPU [Family MPU]
分类和应用:
文件页数/大小: 326 页 / 1089 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8018x Family  
MPU User Manual  
152  
c. Poll the RE bit in CNTR until RE = 0.  
d. Read the receive data from TRDR.  
e. Repeat steps 2 to 4 for each receive data byte.  
Receive–Interrupts  
a. Poll the RE bit in CNTR until RE is 0.  
b. Set the RE and EIE bits in CNTR to 1.  
c. When the receive interrupt occurs read the receive data from  
TRDR.  
d. Set the RE bit in CNTR to 1.  
e. Repeat steps 3 and 4 for each receive data byte.  
CSI/O Operation Timing Notes  
Transmitter clocking and receiver sampling timings are different from  
internal and external clocking modes. Figure 59 to Figure 62 illustrate  
CSI/O Transmit/Receive Timing.  
The transmitter and receiver is disabled TE and RE = 0) when  
initializing or changing the baud rate.  
CSI/O Operation Notes  
Disable the transmitter and receiver (TE and RE = 0) before  
initializing or changing the baud rate. When changing the baud rate  
after completion of transmission or reception, a delay of at least one  
bit time is required before baud rate modification.  
When RE or TE is cleared to 0by software, a corresponding receive  
or transmit operation is immediately terminated. Normally, TE or RE  
is only cleared to 0when EF is 1.  
Simultaneous transmission and reception is not possible. Thus, TE  
and RE are not both 1at the same time.  
UM005001-ZMP0400  
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