Z8018x Family
MPU User Manual
137
Bit
Position Bit/Field R/W Value Description
2
1
0
Break
Feature
Enable
R/W
R/W
R/W
0
1
Break Feature Enable On
Break Feature Enable Off
Break
Detect
(RO)
0
1
Break Detect On
Break Detect Off
Send
Break
0
1
Normal Xmit
Drive TXA Low
Each ASCI channel control register B configures multiprocessor mode,
parity and baud rate selection.
ASCI0 Time Constant Low Register (I/O Address: 1AH) (Z8S180/L180-Class Processors
Only)
Bit
7
R/W
0
6
R/W
0
5
R/W
0
4
R/W
0
3
R/W
0
2
R/W
0
1
R/W
0
0
R/W
0
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
ASCI0 Time Constant High Register (I/O Address: 1BH) (Z8S180/L180-Class Processors
Only)
Bit
7
R/W
0
6
R/W
0
5
R/W
0
4
R/W
0
3
R/W
0
2
R/W
0
1
R/W
0
0
R/W
0
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
UM005001-ZMP0400
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