Z8018x Family
MPU User Manual
136
Bit
Position Bit/Field R/W Value Description
0
Send
Break
R/W
0
1
Normal Xmit
Drive TXA Low
Each ASCI channel control register B configures multiprocessor mode,
parity and baud rate selection.
ASCI1 Extension Control Register (I/O Address: 13H) (Z8S180/L180-Class Processors
Only)
Bit
7
6
5
4
3
2
1
0
Bit/Field
RDRF
Int
Inhibit
Reserved
X1 Bit
Clk
ASCI1
BRG1
Mode
Break
Feature
Enable
Break
Detect
(RO)
Send
Break
R/W
R/W
0
?
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field R/W Value Description
7
RDRF
Interrupt
Inhibit
R/W
0
1
RDRF Interrupt Inhibit On
RDRF Interrupt Inhibit Off
6–5
4
Reserved
?
0
Reserved. Must be 0
X1 Bit
Clk
R/W
0
1
CKA1 /16 or /64
CKA1 is bit clock
ASCI1
3
BRG1
Mode
R/W
0
1
As S180
Enable 16-bit BRG counter
UM005001-ZMP0400
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