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Z8018008VSC 参数 Datasheet PDF下载

Z8018008VSC图片预览
型号: Z8018008VSC
PDF下载: 下载PDF文件 查看货源
内容描述: 家庭MPU [Family MPU]
分类和应用:
文件页数/大小: 326 页 / 1089 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8018x Family  
MPU User Manual  
112  
4. Specify whether DREQ1 is level- or edge- sense in the DMS1 bit in  
DCNTL.  
5. Enable or disable DMA termination interrupt with the DIE1 bit in  
DSTAT.  
6. Program DE1 = 1 (with DWE1 = 0 in the same access) in DSTAT  
and the DMA operation with the external I/O device begins using the  
external DREQ1 input and TEND1 output.  
DMA Bus Timing  
When memory (and memory mapped I/O) is specified as a source or  
destination, MREQ goes Low during the memory access. When I/O is  
specified as a source or destination, IORQ goes Low during the I/O access.  
When I/O (and memory mapped I/O) is specified as a source or  
destination, the DMA timing is controlled by the external DREQ input  
and the TEND output indicates DMA termination  
External I/O devices may not overlap addresses with internal I/O  
and control registers, even using DMA.  
Note:  
For I/O accesses, one Wait State is automatically inserted. Additional  
Wait States can be inserted by programming the on-chip wait state  
generator or using the external WAIT input.  
For memory mapped I/O accesses, this automatic I/O Wait State  
is not inserted.  
Note:  
For memory to memory transfers (channel 0 only), the external DREQ0  
input is ignored. Automatic DMA timing is programmed as either  
BURST or CYCLE STEAL.  
When a DMA memory address carry/borrow between bits A15 and A16  
of the address bus occurs (crossing 64KB boundaries), the minimum bus  
UM005001-ZMP0400  
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