Z8018x Family
MPU User Manual
113
cycle is extended to 4 clocks by automatic insertion of one internal Ti
state.
DMAC Channel Priority
For simultaneous DREQ0 and DREQ1 requests, channel 0 has priority
over channel 1. When channel 0 is performing a memory to/from memory
transfer, channel 1 cannot operate until the channel 0 operation has
terminated. If channel 1 is operating, channel 0 cannot operate until
channel 1 releases control of the bus.
DMAC and BUSREQ, BUSACK
The BUSREQ and BUSACK inputs allow another bus master to take
control of the Z8X180 bus. BUSREQ and BUSACK take priority over the
on-chip DMAC and suspends DMAC operation. The DMAC releases the
bus to the external bus master at the breakpoint of the DMAC memory or
I/O access. Since a single byte DMAC transfer requires a read and a write
cycle, it is possible for the DMAC to be suspended after the DMAC read,
but before the DMAC write. Hence, when the external master releases the
Z8X180 bus (BUSREQ High), the on-chip DMAC correctly continues
the suspended DMA operation.
UM005001-ZMP0400
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