Z8018x Family
MPU User Manual
110
DREQ0 for ASCI transmission and reception respectively. To initiate
memory to/from ASCI DMA transfer, perform the following operations:
1. Load the source and destination addresses into SAR0 and DAR0
Specify the I/O (ASCI) address as follows:
a. Bits A0–A7 must contain the address of the ASCI channel
transmitter or receiver (I/O addresses 6H-9H).
b. Bits A8–A15 must equal 0.
c. Bits SAR17–SAR16 must be set according to Table 16 to enable
use of the appropriate ASCI status bit as an internal DMA
request.
Table 16. DMA Transfer Request
SAR18 SAR17 SAR16 DMA Transfer Request
X
X
X
X
0
0
1
1
0
1
0
1
DREQ0
RDRF (ASCI channel 0)
RDRF (ASCI channel 1)
Reserved
Note: X = Don’t care
DAR18 DAR17 DAR16 DMA Transfer Request
X
X
X
X
0
0
1
1
0
1
0
1
DREQ0
TDRE (ASCI channel O)
TDRE (ASCI channel 1)
Reserved
Note: X = Don’t care
UM005001-ZMP0400
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