eZ80L92 MCU
Product Specification
84
Table 33. Timer Data Registers—Low Byte (TMR0_DR_L = 0081h,
TMR1_DR_L = 0084h, TMR2_DR_L = 0087h, TMR3_DR_L = 008Ah,
TMR4_DR_L = 008Dh, or TMR5_DR_L = 0090h)
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
CPU Access
Note: R = Read only.
R
R
R
R
R
R
R
R
Bit
Position
Value Description
[7:0]
TMRx_DR_L
00h–FFh These bits represent the Low byte of the 2-byte timer data
value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]}. Bit 7 is bit 7
of the 16-bit timer data value. Bit 0 is bit 0 (lsb) of the 16-bit
timer data value.
Timer Data Registers—High Byte
This Read-Only register returns the High byte of the current count value of the selected
timer. The Timer Data Register—High Byte, detailed in Table 34, can be read while the
timer is in operation. Reading the current count value does not affect timer operation. To
read the 16-bit data of the current count value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]},
first read the Timer Data Register—Low Byte and then read the Timer Data Regis-
ter—High Byte. The Timer Data Register—High Byte value is latched when a Read of the
Timer Data Register—Low Byte occurs.
Note:
The timer data registers and timer reload registers share the same address space.
Table 34. Timer Data Registers—High Byte (TMR0_DR_H = 0082h,
TMR1_DR_H = 0085h, TMR2_DR_H = 0088h, TMR3_DR_H = 008Bh,
TMR4_DR_H = 008Eh, or TMR5_DR_H = 0091h)
Bit
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Reset
R
R
R
R
R
R
R
R
CPU Access
Note: R = Read only.
PS013015-0316
Programmable Reload Timers
ZILOG [ ZILOG, INC. ]
