eZ80L92 MCU
Product Specification
57
Bus Mode
Controller
eZ80 Bus Mode
Signals (Pins)
Intel Bus
Signal Equvalents
INSTRD
RD
ALE
RD
WR
WR
WAIT
READY
MREQ
MREQ
IORQ
IORQ
ADDR[23:0]
ADDR[23:0]
ADDR[7:0]
Multiplexed
Bus
Controller
DATA[7:0]
DATA[7:0]
®
Figure 9. Intel Bus Mode Signal and Pin Mapping
Intel Bus Mode (Separate Address and Data Buses)
During Read operations with separate address and data buses, the Intel Bus Mode employs
4 states (T1, T2, T3, and T4) as described in Table 16.
Table 16. Intel® Bus Mode Read States (Separate Address and Data Buses)
STATE T1 The Read cycle begins in State T1. The CPU drives the address onto the
address bus and the associated Chip Select signal is asserted. The CPU
drives the ALE signal High at the beginning of T1. During the middle of T1,
the CPU drives ALE Low to facilitate the latching of the address.
STATE T2 During State T2, the CPU asserts the RD signal. Depending on the
instruction, either the MREQ or IORQ signal is asserted.
PS013015-0316
Chip Selects and Wait States
ZILOG [ ZILOG, INC. ]
