eZ80L92 MCU
Product Specification
56
T
T1
T2
T3
CLK
System Clock
ADDR[23:0]
DATA[7:0]
CSx
RD
WAIT
WR
MREQ
or IORQ
®
Figure 8. Z80 Bus Mode Write Timing Example
Intel Bus Mode
Chip selects configured for Intel Bus Mode modify the eZ80 bus signals to duplicate a
four-state memory transfer similar to that found on Intel-style microprocessors. The bus
signals and ZLP12840 pins are mapped as illustrated in Figure 9. In Intel Bus Mode, the
user can select either multiplexed or non-multiplexed address and data buses. In non-mul-
tiplexed operation, the address and data buses are separate. In multiplexed operation, the
lower byte of the address, ADDR[7:0], also appears on the data bus, DATA[7:0], during
State T1 of the Intel Bus Mode cycle. During multiplexed operation, the lower byte of the
address bus also appears on the address bus in addition to the data bus.
PS013015-0316
Chip Selects and Wait States
ZILOG [ ZILOG, INC. ]
