eZ80L92 MCU
Product Specification
187
Table 108. Block Transfer and Compare Instructions
Mnemonic
LDD (LDDR)
LDI (LDIR)
Instruction
Load and Decrement (with Repeat)
Load and Increment (with Repeat)
Table 108. Exchange Instructions
Mnemonic
EX
Instruction
Exchange registers
EXX
Exchange CPU Multibyte register banks
Table 108. Input/Output Instructions
Mnemonic
IN
Instruction
Input from I/O
IN0
Input from I/O on Page 0
IND (INDR)
INDRX
Input from I/O and Decrement (with Repeat)
Input from I/O and Decrement Memory Address
with Stationary I/O Address
IND2 (IND2R)
INDM (INDMR)
INI (INIR)
Input from I/O and Decrement (with Repeat)
Input from I/O and Decrement (with Repeat)
Input from I/O and Increment (with Repeat)
INIRX
Input from I/O and Increment Memory Address
with Stationary I/O Address
INI2 (INI2R)
INIM (INIMR)
OTDM (OTDMR)
OTDRX
Input from I/O and Increment (with Repeat)
Input from I/O and Increment (with Repeat)
Output to I/O and Decrement (with Repeat)
Output to I/O and Decrement Memory Address
with Stationary I/O Address
OTIM (OTIMR)
OTIRX
Output to I/O and Increment (with Repeat)
Output to I/O and Increment Memory Address
with Stationary I/O Address
OUT
Output to I/O
PS013015-0316
eZ80® CPU Instruction Set
ZILOG [ ZILOG, INC. ]
