ZL50022
Data Sheet
External Read/Write Address: 006AH
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R3
R3
R3
ML
R3
R2
R2
R2
ML
R2
R1
R1
R1
ML
R1
R0
R0
R0
ML
R0
MML
MMU
MU
MML
MMU
MU
MML
MMU
MU
MML
MMU
MU
Bit
Name
Description
11
10
9
R2MML
Reference 2 Multi-period Lower Limit Mask Bit
When this bit is high, it masks the multi-period lower limit check (or forces pass) for
REF2.
R2MMU
R2ML
Reference 2 Multi-period Upper Limit Mask Bit
When this bit is high, it masks the multi-period upper limit check (or forces pass) for
REF2.
Reference 2 Single-period Lower Limit Mask Bit
When this bit is high, it masks the single-period lower limit check (or forces pass) for
REF2.
8
R2MU
Reference 2 Single-period Upper Limit Mask Bit
When this bit is high, it masks the single-period upper limit check (or forces pass) for
REF2.
7
R1MML
R1MMU
R1ML
Reference 1 Multi-period Lower Limit Mask Bit
When this bit is high, it masks the multi-period lower limit check (or forces pass) for
REF1.
6
Reference 1 Multi-period Upper Limit Mask Bit
When this bit is high, it masks the multi-period upper limit check (or forces pass) for
REF1.
5
Reference 1 Single-period Lower Limit Mask Bit
When this bit is high, it masks the single-period lower limit check (or forces pass) for
REF1.
4
R1MU
Reference 1 Single-period Upper Limit Mask Bit
When this bit is high, it masks the single-period upper limit check (or forces pass) for
REF1.
3
R0MML
R0MMU
R0ML
Reference 0 Multi-period Lower Limit Mask Bit
When this bit is high, it masks the multi-period lower limit check (or forces pass) for
REF0.
2
Reference 0 Multi-period Upper Limit Mask Bit
When this bit is high, it masks the multi-period upper limit check (or forces pass) for
REF0.
1
Reference 0 Single-period Lower Limit Mask Bit
When this bit is high, it masks the single-period lower limit check (or forces pass) for
REF0.
Table 42 - Reference Mask Register (RMR) Bits (continued)
76
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
