ZL50022
Data Sheet
PBGA Pin
Number
LQFPPin
Number
Pin Name
Description
G15, G14,
E15, F14
102, 106,
110, 112
FPo0 - 3
ST-BUS/GCI-Bus Frame Pulse Outputs 0 to 3 (5 V-Tolerant
Three-state Outputs)
FPo0: 8 kHz frame pulse corresponding to the 4.096 MHz output
clock of CKo0.
FPo1: 8 kHz frame pulse corresponding to the 8.192 MHz output
clock of CKo1.
FPo2: 8 kHz frame pulse corresponding to 16.384 MHz output
clock of CKo2.
FPo3: Programmable 8 kHz frame pulse corresponding to
4.096 MHz, 8.192 MHz, 16.384 MHz, or 32.768 MHz output clock
of CKo3.
In Divided Slave modes, the frame pulse width of FPo0 - 3 cannot
be narrower than the input frame pulse (FPi) width.
H14, D11
F15
100, 104
108
FPo_OFF0 - 1 Generated Offset Frame Pulse Outputs 0 to 1 (5 V-Tolerant
Three-state Outputs)
Individually programmable 8 kHz frame pulses, offset from the
output frame boundary by a programmable number of channels.
FPo_OFF2
or
Generated Offset Frame Pulse Output 2 or 19.44 MHz Frame
Pulse Output (5 V-Tolerant Three-state Output)
As FPo_OFF2, this is an individually programmable 8 kHz frame
pulse, offset from the output frame boundary by a programmable
number of channels.
FPo5
By programming the FP19EN (bit 10) of FPOFF2 register to high,
this signal becomes FPo5, a non-offset frame pulse corresponding
to the 19.44 MHz clock presented on CKo5. FPo5 is only available
in Master mode or when the SLV_DPLLEN bit in the Control
Register is set high while the device is in one of the slave modes.
B7, C7, B5,
J6, D6, H5
170, 172,
174, 227,
176, 221
CKo0 - 5
ST-BUS/GCI-Bus Clock Outputs 0 to 5 (5 V-Tolerant
Three-state Outputs)
CKo0: 4.096 MHz output clock.
CKo1: 8.192 MHz output clock.
CKo2: 16.384 MHz output clock.
CKo3: 4.096 MHz, 8.192 MHz, 16.384 MHz or 32.768 MHz
programmable output clock.
CKo4: 1.544 MHz or 2.048 MHz programmable output clock.
CKo5: 19.44 MHz output clock
See Section 6.0 on page 24 for details. In Divided Slave mode, the
frequency of CKo0 - 3 cannot be higher than input clock (CKi).
CKo4 and CKo5 are only available in Master mode or when the
SLV_DPLLEN bit in the Control Register is set high while the
device is in one of the slave modes.
16
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
