ZL50022
Data Sheet
PBGA Pin
Number
LQFPPin
Number
Pin Name
Description
K3
234
TMS
Test Mode Select (5 V-Tolerant Input with Internal Pull-up)
JTAG signal that controls the state transitions of the TAP controller.
This pin is pulled high by an internal pull-up resistor when it is not
driven.
L4
L3
238
239
TCK
Test Clock (5 V-Tolerant Schmitt-Triggered Input with Internal
Pull-up)
Provides the clock to the JTAG test logic.
TRST
Test Reset (5 V-Tolerant Input with Internal Pull-up)
Asynchronously initializes the JTAG TAP controller by putting it in
the Test-Logic-Reset state. This pin should be pulsed low during
power-up to ensure that the device is in the normal functional
mode. When JTAG is not being used, this pin should be pulled low
during normal operation.
M3
G5
240
212
TDi
TDo
Test Serial Data In (5 V-Tolerant Input with Internal Pull-up)
JTAG serial test instructions and data are shifted in on this pin.
This pin is pulled high by an internal pull-up resistor when it is not
driven.
Test Serial Data Out (5 V-Tolerant Three-state Output)
JTAG serial data is output on this pin on the falling edge of TCK.
This pin is held in high impedance state when JTAG is not
enabled.
B12, B13,
C10, C11,
F13, G4,
K12
80, 105,
150, 151,
152, 153,
210
IC_OPEN
Internal Test Mode (5 V-Tolerant Input with Internal Pull-down)
These pins may be left unconnected.
C13, G3
144, 208
IC_GND
NC
Internal Test Mode Enable (5 V-Tolerant Input)
These pins MUST be low.
A8, A9, A14,
A15, E10,
M2, N2, P2,
P16, R2,
61, 62,
63, 64,
65, 66,
No Connect
These pins MUST be left unconnected.
67, 68,
R16, T6, T7,
T8, T9, T10,
T11, T12,
T13, T14,
T15
134, 135,
136, 137,
138, 139,
140, 215,
219, 225,
229, 236,
237
14
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
