ZL50022
Data Sheet
PBGA Pin
Number
LQFPPin
Number
Pin Name
Description
M14, R13
46, 48
MODE_4M0,
MODE_4M1
4M Input Clock Mode 0 to 1 (5V-Tolerant Input with internal
pull-down) These two pins should be tied together and are
typically used to select CKi = 4.096MHz operation. See Table 7,
“ZL50022 Operating Modes” on page 38 for a detailed explanation.
See Table 17, “Control Register (CR) Bits” on page 53 for CKi and
FPi selection using the CKIN1 - 0 bits.
D12
107
OSC_EN
Oscillator Enable (5 V-Tolerant Input with Internal Pull-down) If
tied high, this pin indicates that there is a 20 MHz external
oscillator interfacing with the device. If tied low, there is no
oscillator and CKi will be used for master clock generation.
If the device is in master mode, an external oscillator is required
and this pin MUST be tied high.
C12
B14
149
148
OSCo
OSCi
Oscillator Clock Output (3.3 V Output)
If OSC_EN = ‘1’, this pin should be connected to a 20 MHz crystal
(See Figure 23 on page 90) or left unconnected if a clock oscillator
is connected to OSCi pin under normal operation (See Figure 24
on page 91). If OSC_EN = 0, this pin MUST be left unconnected.
Oscillator Clock Input (3.3 V Input)
If OSC_EN = ‘1’, this pin should be connected to a 20 MHz crystal
(See Figure 23 on page 90) or to a clock oscillator under normal
operation (See Figure 24 on page 91). If OSC_EN = 0, this pin
MUST be driven high or low by connecting either to VDD_IO or to
ground.
E9, D8, B8,
D7
161, 164,
166, 168
REF0 - 3
DPLL Reference Inputs 0 to 3 (5 V-Tolerant Schmitt-Triggered
Inputs)
If the device is in Master mode, these input pins accept 8 kHz,
1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz or
19.44 MHz timing references independently. One of these inputs is
defined as the preferred or forced input reference for the DPLL.
The Reference Change Control Register (RCCR) selects the
control of the preferred reference.These pins are ignored if the
device is in slave mode unless SLV_DPLLEN (bit 13) in the
Control Register (CR) is set. When these input pins are not in use,
they MUST be driven high or low by connecting either to VDD_IO or
to ground.
D9, E8, C8,
E7
159, 163,
165, 167
REF_FAIL0 - 3 Failure Indication for DPLL References 0 to 3 (5 V-Tolerant
Three-state Outputs)
These output pins are used to indicate input reference failure when
the device is in master mode.
If REF0 fails, REF_FAIL0 will be driven high.
If REF1 fails, REF_FAIL1 will be driven high.
If REF2 fails, REF_FAIL2 will be driven high.
If REF3 fails, REF_FAIL3 will be driven high.
If the device is in slave mode, these pins are driven low, unless
SLV_DPLLEN (bit 13) in the Control Register (CR) is set.
15
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
