ZL50022
Data Sheet
1.0 Pinout Diagrams
1.1 BGA Pinout
1
2
3
4
5
6
7
8
9
10
STio22
FPi
11
STio23
CKi
12
13
14
15
16
A
B
A
B
VSS
STi29
STi10
STi9
STi28
STi5
STi27
STi4
STi25
CKo2
STi6
STi2
VSS
STi26
STi0
STi1
CKo4
STi24
CKo0
CKo1
REF3
NC
NC
STio21
STio20
NC
NC
VSS
VDD_
COREA
IC_
IC_
STi31
STi30
STi17
STi16
STi19
REF2
OSCi
VSS
ODE
STio19
OPEN
OPEN
REF_
FAIL2
IC_
IC_
C
D
E
F
C
D
E
F
VSS
STi7
VSS
OSCo IC_GND
STio15
STio14
FPo2
STio18
OPEN
OPEN
REF_
FAIL0
FPo_
OFF1
OSC_
STio13
EN
STi11
STi14
STi15
VDD_IO
STi8
STi3
REF1
VSS
NC
VDD_IO
STio12
FPo3
FPo1
STio16
VDD_
CORE
REF_
FAIL3
REF_
FAIL1
VDD_
CORE
VDD_IO
STi13
REF0
VSS
VSS
VSS
VSS
VSS
VSS
D10
D11
D14
D12
NC
VSS
VDD_IO
A12
A9
VDD_IO
STio17
VDD_
CORE
VDD_
CORE
VDD_
CORE
VDD_
CORE
IC_
FPo_
OFF2
STi12
VDD_IO
TDo
VSS
VSS
VSS
VSS
VSS
VSS
D6
STOHZ15
STOHZ14
STOHZ12
STOHZ13
STOHZ11
STOHZ10
STOHZ9
OPEN
IC_
G
H
G
H
STi18 RESET IC_GND
VDD_IO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD_IO
A13
A10
FPo0
A11
OPEN
VDD_
COREA
FPo_
OFF0
STi21
VSS
VSS
CKo5
VSS
VSS
A7
J
J
STi20 VDD_IOA VDD_IOA
VSS
VSS
TCK
D0
CKo3
VDD_IO
A3
A4
A5
A8
A2
A6
VDD_
COREA
IC_
K
K
STi22
STi23
STio25
STio24
STio26
STio27
VSS
VSS
TMS
TRST
TDi
VDD_IO
A0
A1
OPEN
VDD_
COREA
VDD_
CORE
VDD_
CORE
VDD_
CORE
VDD_
CORE
L
M
N
L
M
N
VDD_IO
VDD_IO
STio10
STio11
STio9
STio8
VDD_
CORE
VDD_
CORE
VDD_
CORE
VDD_
CORE
MOT
MODE_
4M0
NC
NC
VSS
VSS
_INTEL
R/W
DTA_
RDY
VDD_IO
STio0 STOHZ3
D1
D5
D3
D4
NC
7
D7
D13
IRQ
D15
NC
STio4
VDD_IO STOHZ5 STOHZ8
_WR
P
R
P
R
NC
VSS
STio1
STio3 STOHZ1
D8
STio5 STOHZ4 STOHZ6
MODE_
VSS
STio6
NC
STOHZ7
STio7
NC
NC
NC
VSS
16
NC
STOHZ0 STio2 STOHZ2
D2
NC
6
D9
CS
NC
11
DS_RD
4M1
T
T
STio28
2
STio29
3
STio31
4
STio30
5
NC
8
NC
NC
1
9
10
12
13
14
15
Note: A1 corner identified by metallized marking.
Note: Pinout is shown as viewed through top of package.
Figure 2 - ZL50022 256-Ball 17 mm x 17 mm PBGA (as viewed through top of package)
11
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
