ZL38001
Data Sheet
1.11 Bypass Control
A PCM bypass function is provided to allow transparent transmission of pcm data through the ZL38001. When the
bypass function is active, pcm data passes transparently from Rin to Rout and from Sin to Sout, with bit-wise
integrity preserved.
When the Bypass function is selected, most internal functions are powered down to provide low power
consumption.
The BYPASS control bit is located in the main control MC register.
1.12 Adaptation Enable/Disable
Adaptation control bits are located in the AEC and LEC control registers. When the ADAPT- bit is set to 1, the
adaptive filter is frozen at the current state. In this state, the device continues to cancel echo with the current echo
model.
When the ADAPT- bit is set to 0, the adaptive filter is continually updated. This allows the echo canceller to adapt
and track changes in the echo path. This is the normal operating state.
1.13 ZL38001 Throughput Delay
In all modes, voice channels always have 2 frames of delay. In ST-BUS/GCI operation, the D and C channels have
a delay of one frame.
1.14 Power Down / Reset
Holding the RESET pin at logic low will keep the ZL38001 device in a power-down state. In this state all internal
clocks are halted, and the DATA1, Sout and Rout pins are tristated.
The user should hold the RESET pin low for at least 200 msec following power-up. This will insure that the device
powers up in a proper state. Following any return of RESET to logic high, the user must wait for 8 complete 8 KHz
frames prior to writing to the device registers. During this time, the initialization routines will execute and set the
ZL38001 to default operation (program execution from ROM using default register values).
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Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
