SP8858
t 1t
CH
S
DATA
FIRST DATA BIT
LAST DATA BIT
2V
t
t
t
t
REP
S
CH
CL
CLOCK
2V
2V
ENABLE
t
E
t
S-EN
t
t
t
t
t
t
= t
1 t MIN
CL
REP
S
CH
= 50ns MIN
= 100ns MIN
= 100ns MIN
= 50ns MIN
= [(31M)N1A]4RF INPUT (Hz)150ns
OR 14REFERENCE (Hz)150ns
WHICHEVER IS APPROPRIATE
(SEE DATA ENTRY AND CONTROL)
CH
CL
E
S-EN
Fig. 4 DATA, CLOCK and ENABLE timing requirements
MODULUS CONTROL
PRESCALER
N / N
A
RF INPUT
COUNTER
4
11
RESET
M
RF INPUT
4(MN1A)
COUNTER
Fig. 5
5