SP8858
MODULUS CONTROL
M
10
11
RF INPUT
RF INPUT
f
PD
A
16/17 OR 8/9
FV
COUNTER
COUNTER
XFV
28
27
CD
RESET
LOCK
DETECT
LOCK
DETECT
PD GAIN
2 BITS
15 BITS
4 BITS
13
F1/F2
F1/F2 22-BIT DATA BUFFER
3 BITS SELECT F1/F2
ACTIVE A
FV
XFV
FR
22 BITS
14
15
16
24
25
25
DATA
CLOCK
RPD
PHASE
DETECTOR
CHARGE
PUMP
CP OUTPUT
CP REF
C1 C2
LSB
24-BIT SHIFT REGISTER
16 BITS
DATA
INTERFACE
XFR
MSB
ENABLE
SELECT R
PD
SENSE
16-BIT REFERENCE BUFFER
PD1
4
5
F
F
*
POWER
DOWN
6
PD
V
REF
BUFFER
DISABLE
PD2
*
REF
SELECT MODULUS
13 BITS
DECODE
XFR
FR
R
DIVIDER
*
F
and F
outputs are reversed by the phase detector
REF
PD
sense bit in the F1/F2 programming word. The pin allocations
shown are correct when the sense bit is low (see Fig. 6).
21
20
CRYSTAL
Fig. 2 SP8858 block diagram
500
400
300
200
GUARANTEED
OPERATING
WINDOW
48/9 MODE
GUARANTEED
OPERATING
WINDOW
TYPICAL
SENSITIVITY
416/17 MODE
100
50
0
0
80
500
750
1000
1500
FREQUENCY (MHz)
Fig. 3 Typical input characteristics and input drive requirements
3
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
