欢迎访问ic37.com |
会员登录 免费注册
发布采购

SP8858IGHPAS 参数 Datasheet PDF下载

SP8858IGHPAS图片预览
型号: SP8858IGHPAS
PDF下载: 下载PDF文件 查看货源
内容描述: 1 · 5GHz的专业合成器 [1·5GHz Professional Synthesiser]
分类和应用:
文件页数/大小: 21 页 / 547 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
 浏览型号SP8858IGHPAS的Datasheet PDF文件第1页浏览型号SP8858IGHPAS的Datasheet PDF文件第3页浏览型号SP8858IGHPAS的Datasheet PDF文件第4页浏览型号SP8858IGHPAS的Datasheet PDF文件第5页浏览型号SP8858IGHPAS的Datasheet PDF文件第6页浏览型号SP8858IGHPAS的Datasheet PDF文件第7页浏览型号SP8858IGHPAS的Datasheet PDF文件第8页浏览型号SP8858IGHPAS的Datasheet PDF文件第9页  
SP8858  
Pin  
Description  
F
PD = M divider output pulses = RF input frequency4(MN1A) when SENSE bit in the programming  
4
word = ‘0’. When SENSE bit = 1, this pin is FREF = R divider output pulses = reference input  
frequency 4R. (see Data Entry and Control description and Fig. 6).  
5
FREF = R divider output pulses when SENSE bit in the programming word = ‘0’. When SENSE  
bit = 1, this pin is FPD = M divider output pulses (see Data Entry and Control description and  
Fig. 6).  
6 (POWER DOWN)  
With this pin held high the device is in the power saving standby mode. The serial interface shift  
register and data buffers remain active at all times so that the device can still be programmed in  
this mode.  
Balanced inputs to the RF preamplifier. For single ended operation the signal is AC coupled into  
pin 11 with pin 10 decoupled to ground or vice-versa.  
10, 11 (RF INPUT)  
13 (F1/F2)  
The logic level on this input determines which of the two words stored in the internal buffers is used  
toreloadtheAandMdividersattheendofthecountcycle. WithF1/F2hightheF1bufferisselected.  
Serial data on this line is clocked into a shift register under control of CLOCK and ENABLE.  
Clocks the data into the shift register.  
14 (DATA)  
15 (CLOCK)  
16 (ENABLE)  
Logichighonthispinallowsdatatobeclockedintotheshiftregisterandthesubsequentfallingedge  
loads the buffer chosen by the LSBs of the programmed word. The clock input is ignored when  
ENABLE is low.  
20 (XTAL 2)  
This pin is the input to a buffer amplifier if an external reference signal is provided. Alternatively,  
the amplifier provides the active element for a reference oscillator if a quartz crystal is connected  
at this point (see Applications).  
Leave open circuit if an external reference is used or connect load capacitors for the chosen crystal  
(see Applications)  
21 (XTAL 1)  
24 (RPD)  
An external resistor connected between this pin and VCC sets the charge pump output current. A  
multiplication factor can also be programmed into the device (see Table 3)  
The phase detector output is a single-ended charge pump sourcing or sinking current to the  
inverting input of an external loop filter.  
25 (CP OUTPUT)  
Connected to the non-inverting input of the loop filter to set the DC bias.  
26 (CP REF)  
27 (LOCK DETECT)  
A current sink into this pin is enabled when the lock detect circuit indicates lock. Used to give  
external indication of phase lock.  
28 (CD)  
A capacitor connected to this point determines the lock detect integrator time constant and can be  
used to vary the sensitivity of the phase lock indicator.  
9 (VCC1), 12 (VEE1)  
18 (VCC2), 19 (VEE2)  
23 (VCC3), 2 (VEE3)  
8 (VCC4), 7 (VEE4)  
Pre-amp and prescaler supply.  
Oscillator supply.  
Charge pump supply.  
ECL supply.  
Table 1 Pin descriptions  
2