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SP8858IGHPAS 参数 Datasheet PDF下载

SP8858IGHPAS图片预览
型号: SP8858IGHPAS
PDF下载: 下载PDF文件 查看货源
内容描述: 1 · 5GHz的专业合成器 [1·5GHz Professional Synthesiser]
分类和应用:
文件页数/大小: 21 页 / 547 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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SP8858  
controlling the dividers without disrupting the loop (and vice  
versa).Thisfacilitycanbeusedtoreducesynthesiserswitching  
time by preparing the non-active buffer prior to the instant of  
switching and can also be used to modify the open loop gain.  
To ensure reliable data is loaded into the dividers the  
internal control circuits ensure that the buffer data can only be  
updated if the remaining M count is greater than 3. Given this  
restriction, the maximum time taken to update the buffer after  
the negative going ENABLE transition (or after F1/F2 has  
been toggled) is:  
APPLICATIONS  
Introduction  
This section provides the basic information required to  
implement a complete digital PLL synthesiser based on the  
SP8858. A typical circuit is shown in Fig. 12 and is available  
on a demonstration PCB, including a serial programmer. The  
demonstrationboardcanbeusedtoevaluatetheSP8858and  
can be readily adapted by the system/RF designer for a  
specific application to aid in rapid prototype development.  
Users of the SP8853 should consult Appendix A for details  
ofthedesignchangesthatarerequiredtoreplacetheSP8853  
with the SP8858.  
[(31M) N1A]/RF input150ns  
where update time is in seconds and RF input is in Hz.  
The time taken to re-program the shift register (F1or F2)  
isdeterminedbytheclockrateandthenumberofbitsrequired  
and is equal to:  
PLL Basics  
A system level specification for a stable radio signal will  
include measures of signal stability such as a single sideband  
phase noise specification and a spurious output specification.  
The power spectrum of the composite RF output signal is  
influenced by a number of factors:  
243tREP1tS1tE (see Fig. 4)  
If the reference buffer is selected (C2 = 1, C1 = 1), only the 16  
LSBsoftheshiftregisterareused.13bitsprovidethedataforthe  
Reference divider. Two bits, PD1 and PD2, control the charge  
pump and the divider output buffer as shown in Table 4.  
Residual phase noise of the dividers  
Active loop filter residual noise  
Feedback divider ratio  
Phase detector gain  
PD2  
PD1  
Result  
VCO signal phase noise and gain  
Reference signal phase noise  
The closed loop root locations (an under damped loop will  
cause a noise peak)  
0
0
FREF and FPD outputs off, charge pump on  
0
1
1
1
0
1
FREF and FPD outputs on, charge pump on  
FREF and FPD outputs on, charge pump off  
Environmental influences such as EMI and power supply  
noise  
FREF and FPD outputs on, charge pump  
disabled by lock detect  
A single-loop synthesiser based around the SP8858 is  
suitable for the synthesis of highly stable, low phase noise  
signals provided each of the points above are carefully  
considered.  
Table 4  
The remaining bit of the Reference word is used to select  
the prescaler modulus. A ‘1’ in this position selects the 8/9  
mode. Note that when the 8/9 mode is selected the A divider  
only requires 3 bits; the 4th bit must be set to ‘0’.  
The block diagram of a simple PLL is shown in Fig. 7.  
To ensure reliable data is loaded into the dividers the  
internal control circuits ensure that the buffer data can only be  
updated if the remaining R count is greater than 1. Given this  
restriction, the maximum time taken to update the buffer after  
the negative going ENABLE transition (or after F1/F2 has  
been toggled) is:  
PHASE  
DETECTOR  
(mA/RAD) K  
LOOP FILTER  
(V/mA)  
VCO  
(RAD/SEC/V)  
PD  
F
O
(Hz) fo(s)  
F
REF  
(Hz)  
K
VCO  
s
(s)  
fi  
F(s)  
1/FREF150ns  
F
(Hz)  
PD  
DIVIDER  
Only 16 bits are required to program the reference buffer,  
therefore reference programming time tREF is:  
4N  
tREF =163tREP1tS1tE (see fig. 4)  
If the Active A mode is programmed (C2=0. C1=1) only the  
four A divider bits are updated at the end of the M count. The  
M divider data, multiplication factor and phase detector sense  
remain unchanged. This can be used to frequency hop to an  
adjacent channel with the programming time reduced to:  
(s)  
f
o
F(s)3K  
3K  
PD  
VCO  
=
CLOSED LOOP RESPONSE =  
OPEN LOOP DC GAIN =  
fi(s)  
s1F(s)3K  
3K /N  
VCO  
PD  
K
3K /N  
VCO PD  
Fig. 7  
Programming time (Active A) = 63tREP1tS1tE  
The basic aim is to phase-lock the VCO signal to a stable  
reference signal, fi(s) and, ideally, set a relatively wide  
closed loop bandwidth and a high DC loop gain  
(KPD3KVCO/N). This combination will ensure that the free-  
running VCO phase noise is attenuated and that both the  
long-term and the short-term stability of the output signal is  
determined by the properties of the reference signal. A wide  
loop bandwidth would also be consistent with the requirement  
of many synthesiser specifications to change frequency and  
regain phase lock within a specified time limit. In practice, the  
following considerations limit the closed loop bandwidth and  
the DC gain and, consequently, limit the extent to which the  
ideal system is achieved:  
Theprogrammingdetailsdiscussedabovearesummarised  
in Fig. 6.  
Lock Detect  
A simple Exclusive-OR phase detector together with an  
integrator and comparator are used to indicate phase lock.  
Capacitor CD on pin 28 sets the integrator time constant  
and hence the sensitivity of the lock detect function. The  
comparator controls a current sink connected to pin 27 which  
can be used together with an external LED or resistor to  
indicate phase lock.  
The lock detect can also be used to disable the charge pump  
by programming PD1 and PD2 of the reference word (Table 4).  
8