P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
2.3.5 Register Map
Note: All 32-bit registers are D-word aligned.
All 16-bit registers are also D-word aligned and right justified.
For the Little Endian CPUs, register offset bit [1,0] are always set to be 00.
For the Big Endian CPUs, register offset bit [1,0] are always set to be 10.
This is a Global Register. CPU is allowed to write the Global Register of all devices by a
single operation.
These registers are reserved for system diagnostic usage only.
I/O Offset
Register Description
Little
Big
Reg. W/R Note:
Endian Endian Size
Device Configuration Registers (DCR)
GCR
Global Control Register
Device Status Register
Signature & Revision Register
ID Register
hF00 hF02 16-bit W/--
hF00 hF02 16-bit --/R
hF10 hF12 16-bit --/R
hF20 hF22 16-bit W/R
hF30 hF32 16-bit W/R
hF40 hF42 16-bit --/R
hF50 hF52 16-bit W/R
DCR0
DCR1
DCR2
DCR3
DCR4
DCR5
Local Control Register
Interface Status Register
Bus Credit Register
Interrupt Controls
ISR
Interrupt Status Register – Unmasked
hF80 hF82 16-bit --/R
hF90 hF92 16-bit --/R
hFA0 hFA2 16-bit W/R
hFB0 hFB2 16-bit W/--
ISRM
IMSK
IAR
Interrupt Status Register – Masked
Interrupt Mask Register
Interrupt Acknowledgment Register
Buffer Memory Interface
MWAR Memory Write Address Register – Single Cycle hE08 hE08 32-bit W/R
MRAR Memory Read Address Register – Single Cycle hE18 hE18 32-bit W/R
MBAR Memory Address Register – Burst Mode
MWBS Memory Write Burst Size (in D-words)
MRBS Memory Read Burst Size (in D-words)
MWDR Memory Write Data Register
hE28 hE28 32-bit W/R
hE40 hE42 16-bit W/R
hE50 hE52 16-bit W/R
hE68 hE68 32-bit W/--
hE6C hE6C 32-bit W/--
hE68 hE68 32-bit --/R
hE6C hE6C 32-bit --/R
MWDX Memory Write Data Register – Byte Swapping
MRDR Memory Read Data Register
MRDX Memory Read Data Register – Byte Swapping
Buffers & Stacks Management
Frame Control Buffers
FCBBA Frame Control Buffer – Base Address
hD00 hD02 16-bit W/R
hD20 hD22 16-bit --/R
hD20 hD22 16-bit W/--
hD30 hD32 16-bit --/R
hD80 hD82 16-bit W/R
hD90 hD92 16-bit W/R
FCBA
FCBR
Frame Control Buffer – Buffer Allocation
Frame Control Buffer – Buffer Release
FCBAG Frame Control Buffer – Buffer Aging Status
FCBSA Frame Ctrl Buffer Stack – Base Address
FCBSL Frame Ctrl Buffer Stack – Size Limit
FCBST Frame Ctrl Buffer Stack – Buffer Low Threshold hDA0 hDA2 16-bit W/R
FCBSS Frame Ctrl Buffer Stack – Allocation Status hDB0 hDB2 16-bit --/R
© 1998 Vertex Networks, Inc.
1999
18
Rev. 4.5 – February
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
