P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
I/O Offset
Little Big
Register Description
Reg. W/R Note:
Endian Endian Size
Buffers & Stacks Management (Continue)
Switch Control Buffers
SCBBA Switch Control Buffer – Base Address
SCBA Switch Control Buffer – Buffer Allocation
hC00 hC02 16-bit W/R
hC20 hC22 16-bit --/R
hC30 hC32 16-bit --/R
hC80 hC82 16-bit W/R
hC90 hC92 16-bit W/R
SCBAG Switch Control Buffer – Buffer Aging Status
SCBSA Switch Ctrl Buffer Stack – Base Address
SCBSL Switch Ctrl Buffer Stack – Size Limit
SCBST Switch Ctrl Buffer Stack – Buffer Low Threshold hCA0 hCA2 16-bit W/R
SCBSS Switch Ctrl Buffer Stack – Allocation Status
hCB0 hCB2 16-bit --/R
MAC Control Tables
MCTA
MAC Control Table – Table Allocation
hB20 hB22 16-bit --/R
MCTR MAC Control Table – Table Release
MCTSA MAC Ctrl Table Stack – Base Address
MCTSS MAC Ctrl Table Stack – Allocation Status
hB20 hB22 16-bit
W/-
hB80 hB82 16-bit W/R
hBB0 hBB2 16-bit --/R
Queue Management
QSBA
MFTA
CINQ
Queue Structure – Base Address
Multicast Frame Table – Base Address
CPU Input Queue
hA00 hA02 16-bit W/R
hA10 hA12 16-bit W/R
hA88 hA88 32-bit W/--
hA88 hA88 32-bit --/R
hA98 hA98 32-bit --/R
hAA8 hAA8 32-bit --/R
hAB8 hAB8 32-bit --/R
COTQ CPU Output Queue
CSQ0
CSQ1
CSQ2
CPU Status Queue – 1st D-word
CPU Status Queue – 2nd D-word
CPU Status Queue – 3rd D-word
CAM Interface
CCWR CAM Command/Data Write Register
h908 h908 32-bit W/--
h928 h928 32-bit --/R
h938 h938 32-bit --/R
CSRL
CSRH
CAM Status/Data Read Register Low
CAM Status/Data Read Register High
HISC Control
HPCR
HMCL
HPRC
HISC Processor Control Register
h980 h982 16-bit W/R
h998 h998 32-bit W/R
h9B0 h9B2 16-bit W/R
HISC Micro-Code Loading Port
HISC Priority Control Register
© 1998 Vertex Networks, Inc.
19
Rev. 4.5 – February
1999
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
