P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
Supported Memory Configurations
Read/Write Chip Select and High Address Bits
Chip #3 Chip #2 Chip #1 Chip #0
# of Total Buffer L_A[19] /
RAM
L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
Chip Size RAM
Chips
Memory L_WE[3]#
Size
64k x 32
128k x 32
256k x32
1
2
4
1
2
4
1
2
256k bytes
512k bytes
----
----
----
----
----
----
----
----
----
----
L_WE[0]# L_OE[0]#
L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
1M bytes L_WE[3]# L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
256k bytes
1M bytes
----
----
----
----
----
----
----
----
----
----
L_WE[0]# L_OE[0]#
L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
2M bytes L_WE[3]# L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
1M bytes L_A[19]
2M bytes L_A[19]
----
----
----
----
----
----
----
----
L_WE[0]# L_OE[0]#
L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
2.2.2 Bus Cycle Waveforms
L_CLK
L_ADSC#
L_CS#
L_A[19:2]
A1
A2
A3
A3+1
A3+2
A3+3
A4
A4+1
A4+2
A4+3
A5
A6
L_WE[3:0]#
L_BWE[3:0]#
L_OE[3:0]#
L_D[31:0] (Wr)
L_D[31:0] (Rd)
D1
D3 D3+1
D3+2
D3+3
D6
D2
D4
D4+1
D4+2
D4+3
D5
Typical Local Memory Access Operations
Note: Refer to manufacturer’s data sheet for detailed timing parameters.
© 1998 Vertex Networks, Inc.
1999
14
Rev. 4.5 – February
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
