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XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
2.4 XpressFlow Bus Interface
à Data Messages for forwarding an Ethernet
frame from receiving port to transmission
port
t Vertex Networks’ optimized XpressFlow Bus
architecture
t Provides 1G bps switching bandwidth
t Full multi bus master structure
t Built-in intelligent bus load regulator for data
traffic balancing
t Allows XpressFlow Engine to communicate
t Provides centralized bus arbitration with two
with Access Controllers via a message pass-
ing protocol
level request priorities
à High priority for Data Messages
à Command Messages for passing control
à Low priority for Command Messages
information between devices
2.4.1 Pin Description
Symbol
Type Name & Functions
CMOS Data Bus Bit [31:0] – a 32-bit synchronous data bus.
S_D[31:0]
I/O-TS
Note: During the system RESET period, Data Bit [31:28] are used as
Processor Interface Configuration bit [0:3]
S_MSGEN# CMOS Message Envelope – encompasses the entire period of a message
I/O-TS
transfer. Targets use the leading edge of this signal to detect the be-
ginning of a message transfer, and to decode the message header for
the intended target(s).
S_EOF#
S_IRDY
CMOS
I/O-TS
End of Frame – only used by frame data transfer messages to identify
the end of frame condition. This signal is synchronous with the Rx
Frame Status word appended to the end of the message.
CMOS Initiator Ready – a normal true signal. When negated, it indicates the
I/O-TS
initiator had asserted wait state(s) in between command words. Target
should use this signal as enable signal for latching the data from the
bus.
S_TABT#
CMOS Target Abort – when asserted, the target had aborted the reception of
I/O-OD
current message on the bus.
CMOS High Priority Request – indicates one or more Bus Requester is re-
I/O-OD
S_HPREQ#
questing for high priority message transfer.
S_REQ[8:1]# CMOS Bus Request [8:1] – Bus Request signals from Access Controllers to
Input
S_GNT[8:1]# CMOS Bus Grant [8:1] – Bus Grant signals from Bus Arbitrator to Bus Re-
Output
Bus Access Arbitrator in XpressFlow Engine
questers
CMOS Bus Overload – when asserted all data forwarding bus bandwidth has
S_OVLD#
Output
been allocated. Cannot support additional load for data forwarding traf-
fic
S_CLK
CMOS XpressFlow Bus Clock – 33MHz system clock
Input
© 1998 Vertex Networks, Inc.
20
Rev. 4.5 – February
1999
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
