MT90826
Data Sheet
Pin Description
Pin # MQFP
Pin # PBGA
Pin # LBGA
Name
Description
12,22,33,54, D5,D6,D7,D8,D9,
D5,D6,D7,E9,
F4,F9,G4,H4,
J6,J7,J8
VDD
+3.3 Volt Power Supply.
66,77,90,101,
112,125,136,
147,157
E4,E10,F4,
F10,G4,G10,
H4,J4,J10,K5,
K6,K7
11,21,32,45,
53,60,65,71,
76,84,89,95,
100,106,111,
117,124,130,
135,141,146,
156
D4,D10,E5,E6,
E7,E8,E9,F5,
F9,G5,G9,H5,
H9,H10,J5,J6,
J7,J8,J9,K4
D4,D9,E5,E6,
E7,E8,F5,F6,
F7,F8,G5,G6,
G7,G8,H5,H6,
H7,H8,J4
Vss
Ground.
34
35
36
N11
M11
N12
M10
M11
L11
TMS
TDI
Test Mode Select (3.3 V Input with
Internal pull-up). JTAG signal that
controls the state transitions of the TAP
controller. This pin is pulled high by an
internal pull-up when not driven.
Test Serial Data In (3.3 V Input with
Internal pull-up). JTAG serial test
instructions and data are shifted in on
this pin. This pin is pulled high by an
internal pull-up when not driven.
TDO
Test Serial Data Out (3.3 V Output).
JTAG serial data is output on this pin
on the falling edge of TCK. This pin is
held in high impedance state when
JTAG scan is not enabled.
37
38
N13
M12
L10
TCK
Test Clock (5 V Tolerant Input).
Provides the clock to the JTAG test
logic.
M12
TRST
Test Reset (3.3 V Input with internal
pull-up). Asynchronously initializes the
JTAG TAP controller by putting it in the
Test-Logic-Reset state. This pin is
pulled by an internal pull-up when not
driven. This pin should be pulsed low
on power-up, or held low, to ensure that
the device is in the normal functional
mode.
42
43
L11
K11
K10
IC1
Internal Connection 1 (3.3 V Input
with internal pull-down). Connect to
V
SS for normal operation.
M13
RESET
Device Reset (5 V Tolerant Input).
This input (active LOW) puts the device
in its reset state which clears the
device internal counters and registers.
10
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
