MT90826
Data Sheet
Changes Summary
The following table captures the changes from the April 2005 issue.
Page
Item
Change
26
Figure 6 “Examples for Input Offset
Delay Timing”
Clarified the mid-point sampling of the 16Mbps input
data.
30
Section 9.0 Initialization of the
MT90826
Added the 600 µs waiting time needed for the APLL
module to be stabilized before starting the next
microprocessor port access cycle.
37
37
38
AC Electrical Characteristics - Serial
Streams for ST-BUS.
Clarified the 16, 8, 4 and 2 Mbps Input Data Sampling
timing.
Figure 8 “ST-BUS Timing for Stream
rate of 16.384 Mbps”
Clarified the input data sampling position at 16 Mbps
data rate.
Figure 9 “ST-BUS Timing for Stream
rate of 8.192 Mbps when CLK =
16.384 MHz”
Added the input data sampling position at 8 Mbps data
rate.
38
39
Figure 10 “ST-BUS Timing for Stream Added the input data sampling position at 4 Mbps data
rate of 4.096 Mbps when CLK =
16.384 MHz”
rate.
Figure 12 “ST-BUS Timing for Stream Added the input data sampling position at 2 Mbps data
rate of 2.048 Mbps when CLK =
16.384 MHz”
rate.
6
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