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MT8870DSR 参数 Datasheet PDF下载

MT8870DSR图片预览
型号: MT8870DSR
PDF下载: 下载PDF文件 查看货源
内容描述: [DTMF Signaling Circuit, CMOS, PDSO18, 0.300 INCH, MS-013AB, SOIC-18]
分类和应用: 光电二极管
文件页数/大小: 29 页 / 626 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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MT8870D/MT8870D-1 ISO2-CMOS  
Applications  
RECEIVER SYSTEM FOR BRITISH TELECOM  
SPEC POR 1151  
t
=(R C )In[V /(V -V )]  
GTP  
P
1
DD  
DD TSt  
The circuit shown in Fig. 9 illustrates the use of  
MT8870D-1 device in a typical receiver system. BT  
Spec defines the input signals less than -34 dBm as  
the non-operate level. This condition can be attained  
by choosing a suitable values of R and R to  
t
=(R C )In(V /V  
)
GTA  
1
1
DD TSt  
R =(R R )/(R +R )  
V
P
1
2
1
2
DD  
C
1
2
1
provide 3 dB attenuation, such that -34 dBm input  
signal will correspond to -37 dBm at the gain setting  
pin GS of MT8870D-1. As shown in the diagram, the  
St/GT  
ESt  
component values of R and C are the guard time  
3
2
R
R
1
2
Notes:  
requirements when the total component tolerance is  
6%. For better performance, it is recommended to  
use the non-symmetric guard time circuit in Fig. 8.  
R =368K 1%  
1
R =2.2M 1%  
2
C =100nF 5%  
1
Figure 8 - Non-Symmetric Guard Time Circuit  
V
DD  
C
1
DTMF  
Input  
C
2
MT8870D-1  
R
1
V
IN+  
DD  
IN-  
GS  
V
St/GT  
ESt  
StD  
Q4  
R
3
R
2
Ref  
INH  
Q3  
PWDN  
OSC 1  
OSC 2  
Q2  
NOTES:  
X
1
R = 102K1%  
Q1  
1
R = 71.5K1%  
2
TOE  
V
SS  
R = 390K1 %  
3
C ,C = 100 nF 5%  
1
2
X = 3.579545 MHz 0.1%  
1
V
= 5.0V 5%  
DD  
Figure 9 - Single-Ended Input Configuration for BT or CEPT Spec  
4-16