MT8870D/MT8870D-1 ISO2-CMOS
18
17
16
15
14
13
12
11
10
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
IN+
IN-
GS
VDD
St/GT
ESt
StD
Q4
Q3
Q2
IN+
IN-
GS
VDD
St/GT
ESt
StD
NC
Q4
Q3
Q2
Q1
VRef
INH
PWDN
OSC1
OSC2
VSS
VRef
INH
PWDN
NC
OSC1
OSC2
VSS
Q1
TOE
9
10
TOE
20 PIN SSOP
18 PIN PLASTIC DIP/SOIC
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
18 20
1
2
3
1
2
3
IN+
IN-
GS
Non-Inverting Op-Amp (Input).
Inverting Op-Amp (Input).
Gain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
4
5
6
4
5
6
V
Reference Voltage (Output). Nominally V /2 is used to bias inputs at mid-rail (see Fig. 6
and Fig. 10).
Ref
DD
INH
Inhibit (Input). Logic high inhibits the detection of tones representing characters A, B, C
and D. This pin input is internally pulled down.
PWDN Power Down (Input). Active high. Powers down the device and inhibits the oscillator. This
pin input is internally pulled down.
7
8
8
9
OSC1 Clock (Input).
OSC2 Clock (Output). A 3.579545 MHz crystal connected between pins OSC1 and OSC2
completes the internal oscillator circuit.
9
10
V
Ground (Input). 0V typical.
SS
10 11
TOE
Three State Output Enable (Input). Logic high enables the outputs Q1-Q4. This pin is
pulled up internally.
11- 12- Q1-Q4 Three State Data (Output). When enabled by TOE, provide the code corresponding to the
14 15
last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high
impedance.
15 17
StD
ESt
Delayed Steering (Output).Presents a logic high when a received tone-pair has been
registered and the output latch updated; returns to logic low when the voltage on St/GT falls
below V
.
TSt
16 18
17 19
Early Steering (Output). Presents a logic high once the digital algorithm has detected a
valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to
return to a logic low.
St/GT Steering Input/Guard time (Output) Bidirectional. A voltage greater than V detected at
TSt
St causes the device to register the detected tone pair and update the output latch. A
voltage less than V
frees the device to accept a new tone pair. The GT output acts to
TSt
reset the external steering time-constant; its state is a function of ESt and the voltage on St.
18 20
V
DD
Positive power supply (Input). +5V typical.
7,
NC
No Connection.
16
4-12
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