欢迎访问ic37.com |
会员登录 免费注册
发布采购

MT8870DSR 参数 Datasheet PDF下载

MT8870DSR图片预览
型号: MT8870DSR
PDF下载: 下载PDF文件 查看货源
内容描述: [DTMF Signaling Circuit, CMOS, PDSO18, 0.300 INCH, MS-013AB, SOIC-18]
分类和应用: 光电二极管
文件页数/大小: 29 页 / 626 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
 浏览型号MT8870DSR的Datasheet PDF文件第1页浏览型号MT8870DSR的Datasheet PDF文件第2页浏览型号MT8870DSR的Datasheet PDF文件第3页浏览型号MT8870DSR的Datasheet PDF文件第5页浏览型号MT8870DSR的Datasheet PDF文件第6页浏览型号MT8870DSR的Datasheet PDF文件第7页浏览型号MT8870DSR的Datasheet PDF文件第8页浏览型号MT8870DSR的Datasheet PDF文件第9页  
MT8870D/MT8870D-1 ISO2-CMOS  
condition is maintained (ESt remains high) for the  
Digit  
ANY  
1
TOE  
L
INH  
X
X
X
X
X
X
X
X
X
X
X
X
X
L
ESt  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
Q
Q
Q
Q
1
4
3
2
validation period (t  
), v reaches the threshold  
GTP  
c
Z
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
Z
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
Z
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
Z
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
(V ) of the steering logic to register the tone pair,  
TSt  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
latching its corresponding 4-bit code (see Table 1)  
into the output latch. At this point the GT output is  
2
activated and drives v to V . GT continues to drive  
c
DD  
3
high as long as ESt remains high. Finally, after a  
short delay to allow the output latch to settle, the  
delayed steering output flag (StD) goes high,  
signalling that a received tone pair has been  
registered. The contents of the output latch are made  
available on the 4-bit output bus by raising the three  
state control input (TOE) to a logic high. The  
steering circuit works in reverse to validate the  
interdigit pause between signals. Thus, as well as  
rejecting signals too short to be considered valid, the  
receiver will tolerate signal interruptions (dropout)  
too short to be considered a valid pause. This facility,  
together with the capability of selecting the steering  
time constants externally, allows the designer to  
tailor performance to meet a wide variety of system  
requirements.  
4
5
6
7
8
9
0
*
#
A
B
L
C
D
A
L
L
H
H
H
H
undetected, the output code  
will remain the same as the  
previous detected code  
B
L
Guard Time Adjustment  
C
D
L
L
In many situations not requiring selection of tone  
duration and interdigital pause, the simple steering  
circuit shown in Figure 4 is applicable. Component  
values are chosen according to the formula:  
Table 1. Functional Decode Table  
L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE  
X = DON‘T CARE  
t
=t +t  
REC DP GTP  
t =t +t  
ID DA GTA  
recommended for most applications, leaving R to be  
selected by the designer.  
The value of t  
is a device parameter (see Figure  
DP  
11) and t  
is the minimum signal duration to be  
REC  
recognized by the receiver. A value for C of 0.1 µF is  
Different steering arrangements may be used to  
select independently the guard times for tone  
t
=(R C )In[V /(V -V )]  
P 1 DD DD TSt  
GTP  
present (t  
) and tone absent (t  
). This may be  
GTP  
GTA  
V
DD  
t
=(R C )In(V /V  
)
necessary to meet system specifications which place  
both accept and reject limits on both tone duration  
and interdigital pause. Guard time adjustment also  
allows the designer to tailor system parameters  
GTA  
1
1
DD TSt  
C
1
R =(R R )/(R +R )  
P
1
2
1
2
St/GT  
ESt  
such as talk off and noise immunity. Increasing t  
REC  
R
R
1
2
improves talk-off performance since it reduces the  
probability that tones simulated by speech will  
maintain signal condition long enough to be  
a) decreasing t  
; (t  
<t  
)
GTP GTP GTA  
registered. Alternatively, a relatively short t  
with  
REC  
a long t  
would be appropriate for extremely noisy  
DO  
environments where fast acquisition time and  
immunity to tone drop-outs are required. Design  
information for guard time adjustment is shown in  
Figure 5.  
t
=(R C )In[V /(V -V )]  
1 1 DD DD TSt  
GTP  
V
DD  
t
=(R C )In(V /V  
)
GTA  
P
1
DD TSt  
C
1
R =(R R )/(R +R )  
P
1
2
1
2
St/GT  
ESt  
R
2
R
1
b) decreasing t  
; (t  
>t  
)
GTA GTP GTA  
Figure 5 - Guard Time Adjustment  
4-14