MT8870D/MT8870D-1 ISO2-CMOS
AC Electrical Characteristics - V =5.0V 5%, V =0V, -40°C ≤ To ≤ +85°C , using Test Circuit shown in Figure 10.
DD
SS
‡
Characteristics
Sym
Min
Typ
Max
Units
Conditions
1
2
Tone present detect time
Tone absent detect time
Tone duration accept
Tone duration reject
t
5
11
4
14
8.5
40
ms Note 1
ms Note 1
ms Note 2
ms Note 2
ms Note 2
ms Note 2
DP
t
0.5
T
I
M
I
N
G
DA
3
t
t
REC
REC
4
20
20
5
Interdigit pause accept
Interdigit pause reject
Propagation delay (St to Q)
t
40
ID
6
t
DO
7
t
8
11
16
µs
µs
µs
ns
TOE=V
TOE=V
TOE=V
PQ
DD
DD
DD
8
O Propagation delay (St to StD)
t
t
12
PStD
U
T
P
U
T
S
9
Output data set up (Q to StD)
3.4
50
QStD
10
Propagation delay (TOE to Q ENABLE)
t
load of 10 kΩ,
50 pF
PTE
11
Propagation delay (TOE to Q DISABLE)
t
300
ns
load of 10 kΩ,
50 pF
PTD
P
D
W
N
12
13
Power-up time
t
t
30
20
ms Note 3
ms
PU
Power-down time
PD
14
15
16
17
18
Crystal/clock frequency
Clock input rise time
Clock input fall time
Clock input duty cycle
Capacitive load (OSC2)
f
3.5759 3.5795 3.5831 MHz
C
C
L
O
C
K
t
t
110
110
60
ns
ns
%
Ext. clock
Ext. clock
Ext. clock
LHCL
HLCL
DC
40
50
CL
C
30
pF
LO
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
*NOTES:
1.
2.
Used for guard-time calculation purposes only.
These, user adjustable parameters, are not device specifications. The adjustable settings of these minimums and maximums
are recommendations based upon network requirements.
3.
With valid tone present at input, t equals time from PDWN going low until ESt going high.
PU
V
DD
C
1
DTMF
Input
C
2
R
1
MT8870D/MT8870D-1
V
IN+
IN-
GS
V
DD
St/GT
ESt
StD
Q4
R
3
R
2
Ref
INH
Q3
PDWN
OSC 1
OSC 2
NOTES:
Q2
X-tal
R ,R =100KΩ 1%
1
2
Q1
R =300KΩ 1%
3
TOE
V
SS
C ,C =100 nF 5%
1
2
X-tal=3.579545 MHz 0.1%
Figure 10 - Single-Ended Input Configuration
4-20
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
