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MT8870DSR 参数 Datasheet PDF下载

MT8870DSR图片预览
型号: MT8870DSR
PDF下载: 下载PDF文件 查看货源
内容描述: [DTMF Signaling Circuit, CMOS, PDSO18, 0.300 INCH, MS-013AB, SOIC-18]
分类和应用: 光电二极管
文件页数/大小: 29 页 / 626 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ISO2-CMOS MT8870D/MT8870D-1  
Power-down and Inhibit Mode  
A logic high applied to pin 6 (PWDN) will power down  
the device to minimize the power consumption in a  
standby mode. It stops the oscillator and the  
functions of the filters.  
MT8870D/  
MT8870D-1  
C
R
1
IN+  
IN-  
1
+
-
Inhibit mode is enabled by a logic high input to the  
pin 5 (INH). It inhibits the detection of tones  
representing characters A, B, C, and D. The output  
code will remain the same as the previous detected  
code (see Table 1).  
C
R
4
2
R
GS  
5
R
3
R
2
Differential Input Configuration  
V
Ref  
The input arrangement of the MT8870D/MT8870D-1  
provides a differential-input operational amplifier as  
Differential Input Amplifier  
C =C =10 nF  
1
2
R =R =R =100 kΩ  
All resistors are 1% tolerance.  
All capacitors are 5% tolerance.  
1
2
4
5
well as a bias source (V ) which is used to bias the  
Ref  
R =60k, R =37.5 kΩ  
3
inputs at mid-rail. Provision is made for connection of  
a feedback resistor to the op-amp output (GS) for  
adjustment of gain. In a single-ended configuration,  
the input pins are connected as shown in Figure 10  
R R  
2
5
R =  
3
R +R  
2
5
R
R
5
VOLTAGE GAIN (A diff)=  
v
1
with the op-amp connected for unity gain and V  
Ref  
1
INPUT IMPEDANCE  
biasing the input at / V . Figure 6 shows the  
2
DD  
differential configuration, which permits the  
2
1
ωc  
2
(Z  
) = 2  
R
+
adjustment of gain with the feedback resistor R .  
INDIFF  
1
5
Crystal Oscillator  
Figure 6 - Differential Input Configuration  
The internal clock circuit is completed with the  
addition of an external 3.579545 MHz crystal and is  
normally connected as shown in Figure 10 (Single-  
Ended Input Configuration). However, it is possible to  
configure several MT8870D/MT8870D-1 devices  
employing only a single oscillator crystal. The  
oscillator output of the first device in the chain is  
coupled through a 30 pF capacitor to the oscillator  
input (OSC1) of the next device. Subsequent devices  
are connected in a similar fashion. Refer to Figure 7  
for details. The problems associated with unbalanced  
loading are not a concern with the arrangement  
shown, i.e., precision balancing capacitors are not  
required.  
To OSC1 of next  
C
MT8870D/MT8870D-1  
X-tal  
OSC2  
OSC1  
OSC1  
OSC2  
C
C=30 pF  
X-tal=3.579545 MHz  
Figure 7 - Oscillator Connection  
Parameter  
Unit  
Resonator  
R1  
L1  
Ohms  
mH  
pF  
10.752  
.432  
C1  
C0  
Qm  
f  
4.984  
37.915  
896.37  
0.2%  
pF  
-
%
Table 2. Recommended Resonator Specifications  
Note: Qm=quality factor of RLC model, i.e., 1/2ΠƒR1C1.  
4-15