MPEG Packet Data Output MT312
9.5 MPEG Packet Data Output Read/Write Registers
9.5.1 Output Data Control. Register 96 (R/W)
Def
hex
NAME
ADR
B7
B6
B5
B4
B3
B2
B1
B0
OP CTRL
96
MANUAL
MOCLK
BKE
RIV
MCL
KINV
EN
TEI
BSO
BA LK[2:0]
R/W
33
B7:
B6:
MANUAL
MOCLK
Manual MOCLK mode selection, see register 97
BKERIV
High = Inverted signal on BKERR output pin.
Low = Normal signal on BKERR output pin.
B5:
MCLKINV
High = Normal signal on MOCLK output pin.
Low = Inverted signal on MOCLK output pin.
For a description of how to use these features, see section 9.1 MPEG Clock Modes on 55.
With MCLKINV = 0, data is clocked out on the positive edge of MOCLK. If MCLKINV = 1, data is clocked out on
the negative edge of MOCLK.
B4:
EN TEI
High = Enable automatic setting of transport error indicator (TEI) bit in MPEG packet
header byte 2 when the block is flagged as uncorrectable by the Reed-Solomon
decoder. See section 8.2 Data output header format - DVB only. (Not used in DSS).
B3:
BSO
High = Bit serial output of the MPEG data on MDO0 pin.
Low = Parallel output of the MPEG data on MDO[7:0] pins.
B2 -0: BA LK[2:0] + 2 = Number of bytes for byte aligner to lock.
The default register value of 3 is equivalent to 5 good sync words.
9.5.2 Monitor Control. Register 103 (R/W)
Def
hex
NAME
ADR
B7
B6
B5
B4
B3
B2
B1
B0
MON CTRL
103
ERR
IND
Reserved
MON CTRL[3:0]
Monitor control
R/W
00
B7:
ERR IND
Error Indicator.
High
BKERR remains high when error free MPEG packets are being output on the MDO[7:0] bus. BKERR
goes low when there is no De-scrambler lock OR on the first byte of a packet where uncorrectable
bytes are detected. BKERR will remain low until error free MPEG packets are being output on the
MDO[7:0] bus.
Low
BKERR remains high when error free MPEG packets are being output on the MDO[7:0] bus.
BKERR goes low on the first byte of a packet where uncorrectable bytes are detected and will remain
low until the 188th byte (DVB) or 130th byte (DSS) has been clocked out.
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