MT312 QPSK Demodulator
6.2.2 QPSK Status. Registers 4 - 5 (R)
Def
hex
NAME
ADR
B7
B6
B5
B4
B3
B2
B1
B0
QPSK STAT H
04
QPSK STATUS[15:8] (high byte)
R
00
B7:
B6:
B5:
B4:
B3:
B2:
B1:
B0:
High = QPSK SNR MSB
High = QPSK SNR LSB
High = QPSK FR LOCK
High = QPSK Timing AGC LOCK
High = QPSK Timing LOCK
High = QPSK Carrier LOCK
High = QPSK Carrier and Timing (CT) Lock
High = QPSK LOCK
Def
hex
NAME
QPSK STAT L
ADR
B7
B6
B5
B4
B3
B2
B1
B0
05
QPSK STATUS[7:0] (low byte)
R
00
B7:
High = QPSK Timing sweep on
High = QPSK Carrier sweep on
Reserved
B6:
B5-0:
6.2.3 Symbol Rate Output. Registers 116 - 117 (R)
Def
hex
NAME
ADR
B7
B6
B5
B4
B3
B2
B1
B0
SYM RAT OP H 116
SYM RAT OP L 117
SYM RAT OP[15:8] Symbol Rate Output (high byte)
SYM RAT OP[7:0] Symbol Rate Output (low byte)
R
R
00
00
SYM RAT OP[15:0] These two bytes contain a positive number that is inversely proportional to the Symbol rate.
The decimation ratio index must also be read from the MONITOR register bits B[7:5] and divided by 32 to
normalise the result.
PLL_CLK *8192
Rs = ---------------------------------------------------------- * 2 -DEC RATIO
SYM_RAT_OP+ 8192
Where: Rs = Symbol rate in MBaud
PLL CLK = PLL clock frequency in MHz
SYM RAT OP = value of registers 116 and 117.
DEC RATIO = MONITOR H[7:5] when MON CTRL[2:0] = 5.
44
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
