Forward Error Correction MT312
7 Forward Error Correction
7.1 Forward Error Correction Read/Write Registers
7.1.1 FEC Interrupt Enable. Register 31 (R/W)
When the bits of this register are set high, they enable an event to generate an interrupt on the pin 57. All
interrupts may be enabled together.
Def
hex
NAME
ADR
B7
B6
B5
B4
B3
B2
B1
B0
IE FEC
31
IE FEC[7:0] Interrupt enable FEC
R/W
00
B7:
B6:
B5:
B4:
B3:
B2:
B1:
High = Enable DiSEqC™ indication on interrupt pin.
High = Enable Byte Align lock lost indication on interrupt pin.
High = Enable Byte Align lock indication on interrupt pin.
High = Enable Viterbi lock lost indication on interrupt pin.
High = Enable Viterbi lock indication on interrupt pin.
High = Enable Viterbi BER monitor period reached indication on interrupt pin.
High = Enable De-scrambler lock lost indication on interrupt pin.
B0:High = Enable De-scrambler lock indication on interrupt pin.
7.1.2 FEC STATUS Output Enable. Register 33 (R/W)
If more than one bit is enabled then the logical-OR combination of the selected status signals will appear on the
STATUS pin 52.
Def
hex
NAME
ADR
B7
B6
B5
B4
B3
B2
B1
B0
FEC STAT EN
33
MOCLK RATIO[3:0]
DS lock BA
lock
VIT
lock
BER R/W
tog
14
B7-4:
MOCLK RATIO[3:0]
MPEG clock ratio - 6. I.e. range is from 6 to 21
see section 9.1.3 on 54.
B3:
B2:
B1:
DS lock
BA lock
VIT lock
High = De-scrambler lock
High = Byte Align lock
High = Viterbi lock. High = Viterbi lock
47
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
