MT312 QPSK Demodulator
6.1.4 Go Command. Register 27 (R/W)
Def
hex
NAME
ADR
B7
B6
B5
B4
B3
B2
B1
B0
GO
27
Reserved
GO
R/W
00
B7-1:
B0:
Reserved - not used.
GO
High = release reset state to start signal capture, automatically reset to zero.
Low = no action.
If this register is read, it will return zero.
6.1.5 QPSK Interrupt Output Enable. Registers 28 - 30 (R/W)
When the bits of these three registers are set high, they enable an event to generate an interrupt on the IRQ
pin 57. All interrupts may be enabled together. These registers do not affect the indication of events in the read
registers 0 - 3.
Def
hex
NAME
ADR
B7
B6
B5
B4
B3
B2
B1
B0
IE QPSK H
28
IE QPSK[23:16] Interrupt enable QPSK (high byte)
R/W
00
B7:
B6:
B5:
B4:
B3:
B2:
B1:
B0:
High = Enable QPSK CT LOCK indication on interrupt pin.
High = Enable QPSK CT UNLOCK indication on interrupt pin.
High = Enable QPSK LOCK indication on interrupt pin.
High = Enable QPSK UNLOCK indication on interrupt pin.
High = Enable QPSK TS LOCK indication on interrupt pin.
High = Enable QPSK TS UNLOCK indication on interrupt pin.
High = Enable QPSK CS LOCK indication on interrupt pin
High = Enable QPSK CS UNLOCK indication on interrupt pin.
Def
hex
NAME
ADR
B7
B6
B5
B4
B3
B2
B1
B0
IE QPSK M
29
IE QPSK[15:8] Interrupt enable QPSK (middle byte)
R/W
00
B7:
B6:
B5:
High = Enable QPSK FE AGC LOCK indication on interrupt pin.
High = Enable QPSK TS AGC LOCK indication on interrupt pin.
High = Enable QPSK TS AGC UNLOCK indication on interrupt pin.
40
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