MA2910
Instruction 9: Repeat Pipeline Register, Counter ¹ Zero
This instruction is similar to instruction 8 except that the
branch address now comes from the pipeline register rather
than the file. In some cases, this instruction may be thought of
as a one-word file extension; that is, by using this instruction, a
loop with the counter can still be performed when subroutines
are nested nine deep. This instruction’s operation is very
similar to that of instruction 8. The differences are that on this
instruction, a failed test condition causes the source of the next
microinstruction address to be the D inputs; and, when the test
condition is passed, this instruction does not perform a POP
because the stack is not being used.
In this example, the REPEAT PIPELINE, COUNTER J
ZERO instruction is instruction 52 and is shown as a single
microinstruction loop. The address in the pipeline register
would be 52. Instruction 51 in this example could be the LOAD
COUNTER AND CONTINUE instruction (number 12). While
the example shows a single microinstruction loop, by simply
changing the address in a pipeline register, multi-instruction
loops can be performed in this manner for a fixed number of
times as determined by the counter.
Figure 13: 10 COND RETURN (CRTN)
Instruction 11: Conditional Jump Pipeline register
address and POP stack.
This instruction provides another technique for loop
termination and stack maintenance. The example shows a
loop being performed from address 55 back to address 51.
The instructions at locations 52,53, and 54 are all conditional
JUMP and POP instructions. At address 52, if the CC input is
LOW, a branch will be made to address 70 and the stack will
be properly maintained via a POP. Should the test fail, the
instruction at location 53 ( the next sequential instruction) will
be executed. Likewise, at address 53, either the instruction at
90 or 54 will be subsequently executed, respective to the test
being passed or failed. The instruction at 54 follows the same
rules, going to either 80 or 55.
An instruction sequence as described here, using the
Conditional Jump Pipeline and POP instruction, is very useful
when several inputs are being tested and the microprogram is
looping waiting for any of the inputs being tested to occur
before proceeding to another sequence of instructions. This
provides the powerful jump-table programming technique at
the firmware level .
Figure 12: 9 REPEAT PL, CNTR ¹ 0 (RPCT)
Instruction 10: Conditional return form Subroutine.
As the name implies, this instruction is used to branch from
the subroutine back to the next microinstruction address
following the subroutine call. Since this instruction is
conditional, the return is performed only if the test is passed.
If the test is failed, the next sequential microinstruction is
performed. This example depicts the use of the conditional
RETURN-FROM-SUBROUTINE instruction in both the
conditional and the unconditional modes.
This example first shows a JUMP-TO-ROUTINE at
instruction location 52 where control is transferred to location
90. At location 93, a conditional RETURN-FROM-
SUBROUTINE instruction is performed. If the test is passed,
the stack is accessed and the program will transfer to the next
instruction at address 53. If the test is failed, the next
microinstruction at address 94 will be executed, the program
will continue to address 97 where the subroutine is complete.
To perform an unconditional RETURN-FROM-SUBROUTINE,
the conditional RETURN-FROM-SUBROUTINE instruction is
executed unconditionally; the microinstruction at address 97 is
programmed to force CCEN HIGH, disabling the test and the
forced PASS causes an unconditional return.
Figure 12: 9 REPEAT PL, CNTR ¹ 0 (RPCT)
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