MA17503
3.4.4 Interrupt Unit Microcode Enable (INTREN)
3.5.2 User Interrupts (INT02N,08N,10N,11N,13N & 15N)
lnput. The Execution Unit provides lNTREN to the lnterrupt
Unit to enable the microcode command interface. When
INTREN is low, microcode instruction bits 4, 5 and 6 (latched
into the lU microcode register at the SYNCLKN high-to-low
transition, if HLDAKN and DMAKN are high) are decoded by
the lU as commands for the FT, NPU discrete, internal DMA
interface, and interrupt vectoring. lNTREN low causes the EU
to extend the machine cycle to six (EU)OSC periods.
lnputs. Each of these user definable interrupts is latched
into the Pl register bits 2, 8, 10, 11, 13, or 15, respectively.
Level 2 is the highest priority and level 15 is the lowest. These
interrupts are maskable and can be disabled.
3.5.3 I/O Registered Interrupts (1011N & 1012N)
Inputs. Each of these interrupts is latched into the Pl
register bits 12 and 14, respectively. Level 12 is higher than
level 14. These interrupts are maskable and can be disabled.
3.4.5 Data Transceiver Direction (DDN)
Output. DDN is provided to control the directionality of the
AD/Data Bus transceivers. DDN is high during data transfers
from the MAS281 to the user system and when it is necessary
to keep the transceivers from driving the MAS281 System AD
Bus. DDN is low during transfers from the user system to the
MAS281.
3.5.4 Fixed-Point Overflow (OVIN)
Input. This interrupt is driven by the MA17501 Execution
Unit and is latched into the Pl register bit 4. The OVlN interrupt
is maskable and can be disabled.
3.5.5 Interrupt Request (IRN)
Cycles during which DDN is high include: memory writes,
outputs, IU implemented Internal l/O command execution
(except Read Configuration Word (RCW)), and all MA17504
MMU(BPU) implemented l/O command execution.
Cycles during which DDN is low include: memory reads
(data portion), inputs (data portion), the Configuration Word
read (identified by CONFWN, low), and during DMA and Hold
cycles (to allow access to the MMU(BPU).
Output. This signal is the logical inclusive OR of the Pl bits
and is used to signal the MA17502 Control Unit that an interrupt
request is pending.
3.6 FAULT INTERFACE
The Interrupt Unit supports 16 registered error condition
flags. Eleven of the faults are directly accessible through
dedicated input pins. A low on any of these fault inputs is
latched into the Fault register (FT) by the high-to-low transition
of SYNCLKN. Once a fault is latched, it can only be cleared by
clearing the entire FT via lnternal l/O command. The latching of
any fault causes the level 1 interrupt to be set. Once set and
subsequently cleared by the microcoded interrupt service
routine, Pl bit one cannot be set again until the FT is cleared via
internal I/O command. Any unused fault inputs must be pulled-
up to VDD.
3.4.6 Control Transceiver Direction (CDN)
Output. CDN is provided to control the directionality of the
Control Bus (consists of DSN, (EU)AS, M/lON, RD/WN, and
IN/OPN) transceivers. CDN is high during all MAS281 directed
machine cycles. CDN drops low only when DMAKN or
HLDAKN is low, indicating the MAS281 has placed the control
bus signals in the high-impedance state. (It is necessary to use
transceivers to buffer the control bus, if a shared MMU(BPU)
architecture is used, to allow the sharing device access to the
MMU(BPU) functions.)
3.6.1 Memory Protection Error (MPROEN)
lnput. A low on this input is used to inform the MAS281 that
an access fault, execute or write protection violation has been
detected. When the MA31751 MMU(BPU) is used with the
MAS281, the MPROEN fault input is provided by the
MMU(BPU). FT bit 0 is set if a MAS281 directed memory cycle
caused the error and bit 1 is set if a DMA device directed
memory cycle caused the error.
Setting FT bit 0 causes PIFN to drop low. This aborts the
MIL-STD-1750A instruction that was executing when the error
occurred and branches execution to the machine error, level 1
interrupt service routine, if the interrupt is not masked. If the
interrupt is masked, execution continues with the next
instruction.
3.5 INTERRUPT INTERFACE
The Interrupt Unit supports 16 levels of prioritised
interrupts, nine of which are accessible to the user system. All
user accessible interrupts are active low, are buffered with
edge detectors to prevent repeat latching of the interrupt, and
are latched into the Pending Interrupt register (Pl) by the high-
to-low transition of SYNCLKN.
The following interrupts do not have dedicated input pins on
the MA17503. Level 1, Machine Error lnterrupt, is driven by the
ORed bits of the Fault register (FT). Levels 7 and 9 are driven
by the overflow of Interval Timers A and B, respectively. The
Internal I/O command, Set Pending Interrupt (SPI), is used to
set interrupt levels 3, 5, and 6 (Floating-Point Overflow,
Executive Call, and Floating-Point Underflow, respectively) via
microcoded execution.
FT bit 0 is not latched during DMA or the Hold state
(DMAKN or HLDAKN low).
3.6.2 Memory Parity Error (MPEN)
lnput. A low on this input indicates a parity error has been
detected during a memory transfer. This fault is latched into FT
bit 2.
3.5.1 Power Down Interrupt (PWRDN)
Input. The PWRDN interrupt is the highest priority interrupt,
level 0, and is latched into Pl bit zero. It is nonmaskable and
cannot be disabled.
3.6.3 Programmed l/O Parity Error (PIOPEN)
lnput. A low on this input indicates a parity error has been
detected during an external l/O transfer. This fault is latched
into FT bit 3.
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