Le58083
Signal Processing Channels (CHx)
Data Sheet
These blocks do the transmission processing for the voice channels. Part of the processing is analog and is interfaced to the VIN
and VOUT pins. The remainder of the processing is digital and is interfaced to the Time Slot Assigner (TSA) block.
SLIC Device Interface (SLI)
This block communicates digitally with the SLIC device circuits. It sends control bits to the SLIC devices to control modes and to
operate LEDs and optocouplers. It also accepts supervision information from the SLIC devices and performs some filtering.
CONNECTION DIAGRAM
121-Pin BGA
L
VIN
4
_1
VIN
4
_2
NC
C5
3
_1
C4
3
_2
DGND
C5
4
_1
C3
4
_2
C7
4
_2
DRA/DD
DXB
K
VOUT
4
_1
VOUT
4
_2
VCCA
C4
3
_1
C3
3
_2
VCCD
C4
4
_1
CD2
4
_2
C6
4
_2
DRB
DXA/DU
J
NC
NC
AGND
C3
3
_1
CD2
3
_2
C7
3
_2
C3
4
_1
CD1
4
_2
C5
4
_2
FS/FSC
TSCB
H
VREF_2
AGND
AGND
CD2
3
_1
CD1
3
_2
C6
3
_2
CD2
4
_1
NC
C4
4
_2
RST
TSCA
G
VREF_1
VCCA
VCCA
CD1
3
_1
C7
3
_1
C5
3
_2
CD1
4
_1
C7
4
_1
INT_2
NC
PCLK/
DCL
F
VIN
3
_1
VIN
2
_2
VIN
3
_2
NC
C6
3
_1
NC
CD1
1
_1
C6
4
_1
INT_1
VCCD
DIO_1/
S1_1
E
VOUT
3
_1
VOUT
2
_2
VOUT
3
_2
CD1
2
_1
NC
C3
2
_2
CD2
1
_1
C5
1
_1
C3
1
_2
DGND
DCLK_1/
S0_1
D
NC
NC
NC
CD2
2
_1
C6
2
_1
C4
2
_2
C3
1
_1
C6
1
_1
C4
1
_2
CS_1/
PG_1
DIO_2/
S1_2
C
NC
NC
NC
C3
2
_1
C7
2
_1
C5
2
_2
C4
1
_1
C7
1
_1
C5
1
_2
CS_2/
PG_2
DCLK_2/
S0_2
B
VOUT
1
_1
VOUT
2
_1
VOUT
1
_2
C4
2
_1
CD1
2
_2
C6
2
_2
VCCD
CD1
1
_2
C6
1
_2
MCLK_1/
E1_1
MCLK_2/
E1_2
A
VIN
1
_1
VIN
2
_1
VIN
1
_2
C5
2
_1
CD2
2
_2
C7
2
_2
DGND
CD2
1
_2
C7
1
_2
CHCLK_1
CHCLK_2
1
2
3
4
5
6
7
8
9
10
11
7
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
