GP4020
Typical GPS Receiver
Figure 3 shows a typical GPS receiver employing a
GP2015 RF front end and a GP4020 correlator.
The ARM7TDMI is object code compatible with all
earlier ARM6 and ARM7 based products. The
ARM7TDMI is a fully static design and as such
consumes dynamic power only when clocked.
The RF section, GP2015, performs down conversion of
the L1 (1575·42MHz) signal for digital baseband
processing. Theresultantsignalisthencorrelatedinthe
GPS correlator within the GP4020 with an internally
generatedreplicaofthesatellitePRNcodetobereceived.
Individual codes for each channel may be selected
independently to enable acquisition and tracking of up
to 12 different satellites simultaneously.
Boot ROM
The GP4020 BOOT ROM contains code which is executed
every time there is a complete system reset (i.e. when main
power has been removed from the GP4020).
The code installed on the BOOT ROM, allows the
GP4020 to undertake either of 2 functions after a
complete reset:
The results of the correlations form the accumulated
data and are transferred to the microprocessor to give
the broadcast satellite data (the Navigation Message)
and to control the software signal tracking.
• Run External Flash EPROM from the EPROM base
address.
• Load into the internal SRAM a unique program via
the UART1 input. This could be used for test
purposes, although the target use of this facility is to
allow for field upgrades of GPS receiver firmware, in
conjunction with a Flash EPROM.
Device Description
The GP4020 is a complete baseband processor for
Navstar GPS C/A code signals. It incorporates a 12-
channel GPS correlator, a Zarlink Firefly MF1
microcontroller core (incorporating the ARM7TDMI
Thumb microprocessor), Real Time Clock, 8KBytes of
on-chip SRAM and a boot ROM. The GP4020 uses a
fully configurable memory interface, allowing the use of
16-bitexternalmemory. AblockdiagramoftheGP4020
is shown in Figure 1.
BµILD Bus
This is a modular bus architecture and specification, via
which all on-chip modules communicate with each
other. These modules can either be bus masters or
slaves.Abusmastercaninitiateabusaccess,generate
addresses and control read or write transfers. A bus
slave responds to a bus master request when selected
by the system address decoder, and may, if required,
assert a wait signal on the bus until the relevant data
transfer has been completed. All internal data transfers
on the module bus are single cycle. The Firefly MF1
micro-controller has three modules that are capable of
operating as Bus masters. These are the ARM7TDMI
Core, DMAC and SSM, described below.
The GP4020 GPS Baseband processor features:
• Firefly MF1 Core including ARM7TDMI
Microprocessor
• 12-channel Navstar GPS C/A code correlator
• 1KByte Onboard Boot ROM
• 8KByte Onboard SRAM
• 8-bit General Purpose I/O
• Debugging Serial Access Ports - JTAG or SSM
• System Timer / Counters
• Real Time Clock
• BSIO: 3-wire serial interface
• Watchdog
BµILD Serial Input Output (BSIO)
• 1Pulse-Per-Second output, with 25ns resolution
• Flexible system Clock Generator - can use clock
source from a crystal or from RF front end TCXO
Thismoduleproducesa2-channel3-wireserialinterface
for up to 2 external ‘Slave’ serial interface devices (e.g.
serial EEPROM). It provides both Micro-wire Interface
and Serial Peripheral Interface (SPI) compatibility.
ARM Processor (ARM7TDMI)
12-Channel Correlator
The ARM7TDMI is a 32-bit RISC microprocessor core
designed by Advanced RISC Machines (ARM). It uses a
series7microprocessorcore,withthefollowingfunctional
extensions:
This module contains 12 channels of PRN code
correlators for spread-spectrum correlation of 12
simultaneous signals. Each channel contains an
independent carrier DCO to allow independent mix
down of a satellite signal to baseband before code
correlation occurs. The correlator is designed to extract
data modulated at a nominal chipping rate of
1·023Mbps, and can be used on both Navstar C/A code
GPS signals and Inmarsat WAAS codes.
• Thumb (16-bit) instruction set
• Debug interface using J-TAG
• Fast Multiplier
• Embedded In-Circuit Emulation capability
9
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
