GP4020
DMA Controller (DMAC)
General Purpose Input Output (GPIO)
Two DMA engines are available on the microcontroller.
These are configured as a pair to provide a memory-to-
memory DMA capability between any 2 locations in the
ARM7TDMI memory space. They may be used
independently for high speed fly-by transfers between
UART1 (or UART2) and either on-chip or off-chip
locations.
This module provides 8 I/O pins, which may be bit or byte
addressedandconfiguredinalatchedortransparentmode.
External Interrupts can be set for edge or level
sensitivity with a polarity option. To minimise interrupt
latency, there is a hard-wired priority scheme for each
channel for both FIQ and IRQ; alternatively this can be
ignored and the priority assessment handled in
software.
Single or multiple byte transfers (Demand or Burst
Mode) are supported and may be word, half word or
byte wide.
Memory/Peripheral Controller (MPC)
Embedded Microcontroller Debug Options
The MPC ensures the correct multiplexing of data is
applied for bus transfers between 8, 16 or 32-bit on-chip
oroff-chipperipherals.Fourdifferentcontiguousmemory
areas are available, each with an address range of
1 MByte, with individually programmable wait and stop
state generation. A SWAP function allows memory area
1,whichisaddressedatsystemreset,tobeswitchedwith
memory area 4. This allows, for example, booting from
ROM and then switching memory area 1 to address
SRAMsothattime-criticalsoftwareandinterruptroutines
can operate from fast memory.
The Firefly MF1 Core incorporates three sophisticated
methods of hardware and software debug. The options
are:
● Embedded ICE, accessed via the ARM7TDMI
JTAG interface (Multi ICE access also possible)
● Angel Debug Monitor
● Logic Analyser coupled with an Inverse Assembler,
accessed via the SSM debug interface
The GP4020 can use any of these options, but special
emphasis has been placed on the Embedded ICE and
Logic Analyser options. The JTAG and SSM debug
interfaces are multiplexed onto the same pins, and can
be selected by setting NICE (pin 84) high for SSM, or
low for JTAG.
Peripheral Control Logic (PCL)
The GP4020 incorporates some specific control logic,
which is used to control a number of functions:
• System Reset Control
• System Power-down, Sleep and Wake-up Control
• System Status and Control Registers
• Signal input/output multiplex control
Firefly MF1 Microcontroller core
TheFireflyMF1MicrocontrollerisanEmbeddedMicro-
controller core developed by Zarlink Semiconductor. It
combines the processing power of the ARM7TDMI
microprocessor with a number of peripheral
components:
RAM
The GP4020 contains 8KBytes (configured as
2K332-bit) of high-speed (6ns) Static RAM. This can
be used for either:
• Direct Memory Access Controller (DMAC)
• Interrupt Controller (INTC)
• Memory Peripheral Controller (MPC), incorporating
Up-Integration Module (UIM)
• Non-volatile storage of GPS data (Almanac,
Ephemeris, Position and Receiver Clock Offset),
while the receiver power is disabled
• System Services Module (SSM)
• System Timer/Counter (SYSTIC)
• Universal Asynchronous Receiver / Transmitter
(UART)
• A High-speed Interrupt Service Routine, while the
GP4020 is powered up
The internal SRAM appears at GP4020 Base Address
0x60000000, served by the MPC Memory Area 4. An
MPCSWAPfunctioncanswapthismemoryspacewith
0x00000000 if required.
Interrupt Controller (INTC)
The ARM7TDMI core accepts two types of interrupt:
Normal (IRQ) and Fast (FIQ). All Interrupts can be
switched between types, depending upon the relative
priorities required. The INTC is the central control logic
that decodes the priority level and handles interrupt
request signals from a total of 8 fixed pre-defined,
internal sources and a number of external sources.
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ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
