GP4020
NOTES (continued):
6.
NICE (pin 84) and NRST (pin 90) control a number of operation modes and a debug on signal multiplex on pins
86 to 90 as follows:
NICE = low
ARM7TDMI in ICE mode.
ARM7TDMI will not access memory unless instructed by the JTAG interface. NTRST
(pin 90) set Low will reset the JTAG.
NICE = High
ARM7TDMI in Normal mode.
ARM7TDMIdoesnoteffecttheresetontheJTAGinteface. However, aresetofFirefly
will also reset the JTAG.
NTRST (pin 90) has a reset and signal-multiplex function, dependent on the state of NICE (pin 84):
(i)
NICE = Low:
JTAG debug signals connected to pins 86, 87, 88, 89 & 90, as follows:
Pin 86 = TCK
Pin 87 = TDI
Pin 88 = TDO
Pin 89 = TMS
Pin 90 = NTRST
=
=
=
=
=
JTAG clock in
JTAG data in
JTAG data out
JTAG mode select in
Active low reset to JTAG interface
(JTAG interface also reset when Firefly MF1 is reset)
(ii)
NICE = High and NTRST = High:
Normal mode of operation for GP4020. System Services Module Broadcast Diagnostic debug output
signals connected to pins 86, 87, 88, 89 as follows:
Pin 86 = bdiag[0]
Pin 87 = bdiag[1]
Pin 88 = bdiag[2]
Pin 89 = bdiag[3]
Diagnostic mode must have been set-up using the Diagnostic Configuration Registers within Firefly MF1.
Refer to Section 8 of Firefly MF1 Core Design Manual (DM5003), from Zarlink Semiconductor, for more
information.
(iii)
NICE = High & NTRST = Low:
Firefly MF1 System Test Control input signals connected to pins 86, 87, 88, 89 as follows:
Pin 86 = Xreq
Pin 87 = XWrite
Pin 88 = Xburst
Pin 89 = XCon
System test inputs are used in Firefly MF1 macrocell test mode for manufacturing test. Refer to Section 2.10
of Firefly MF1 Core Design Manual (DM5003), from Zarlink Semiconductor, for more information.
Glossary:
1PPS
1 Pulse Per Second
ICE
In Circuit Emulation
ARM®
ARM7TDMI™
Advanced RISC Machines
ARM7 microprocessor with Thumb,
Debug,fastMultiplierandICEBreaker
Extensions
BusforµControllerIntegrationinLow-
Power Designs
BµILD bus system clock
BµILD Serial Input / Output
12-channel Correlator
INTC
MPC
PCL
Interrupt Controller
Memory Peripheral Controller
Peripheral Control Logic
Phase Locked Loop
Random Access Memory
Read Only Memory
PLL
BµILD
RAM
ROM
RTC
SCG
SSM
SYSTIC
TIC
B_CLK
BSIO
CORR
DMAC
Firefly MF1
Real Time Clock
System Clock Generator
System Services Module
System Timer / Counter module
Timer / Counter
Direct Memory Access Controller
Zarlink
Semiconductor
microcontroller cell, based on
ARM7TDMI, DMAC, INTC, MPC,
SYSTIC and UART
General Purpose Input / Output
Global Positioning System
UART
Universal Asynchronous Receiver/
Transmitter
Up-Integration Module
Watchdog
UIM
WDOG
GPIO
GPS
7
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
