GP4020
Electrical Characteristics (continued)
Value
Min. Typ. Max.
Units
Conditions
Characteristic
Symbol
40MHz Low Level Differential Input
Input voltage bias
Differential input voltage
Input differential hysteresis
Input clock frequency
Input capacitance
V
mV
mV
MHz
pF
VDBIAS
VDIFIN
VDIFHYS
FDIFIN
0
100
12
1·715
Min. VDD = 3·0V Note 1
24
150
40
5
40MHz from RF front end
Not including package
CDIFIN
ns
Power-on delay
Processor Clock Oscillator
Frequency
Start up time
Mark:space
150
16
MHz
ms
%
FPRXIN
TPRXSU
10
Correct external components
Across frequency range
Across all conditions
10
50
45
55
mA/V
kΩ
kΩ
Transconductance
Output impedance
Feedback resistance
Phase Locked Loop
Input frequency
gm
ZO
RF
1·0
2·24
93
220
4·4
MHz
MHz
FPLLIN
FPLLOUT
10
10
20
250
Output frequency
Canbedivideddownby1,2,4or
8 for optimal BµlLD_CLK freq.
%
Duty cycle
45
50
55
ns
Phasealignmentoffset(fallingedges
of CLKINB, CLKFBKB)
Phase Alignment Jitter
Phase Jitter
CLKINB to CLKOUTB delay
PLL Settling Time
+-0·2
ns
ns
ns
µs
+-0·25
+-0·15
Note 2
Cycle-cycle edge jitter Note 2
In clock bypass mode
In clock synchronisation mode
0·43
147
TPLLSET
Real Time Clock
kHz
ms
µA/V
MΩ
MΩ
Crystal frequency
Start up time
Transconductance
Output impedance
FRTC
32·768
400
9·56
422
Correct external components
Across frequency range
TRTCSTART
GMRTC
ZORTC
Feedback resistance
RFRTC
10
External component
BµILD Serial Input / Output (BSIO)
3-wire Bus Interface
BSIO_CLK output frequency
Serial clock output low period
Serial clock output high period
Serial clock output rise time
Serial clock output fall time
Serial data output delay
Serial enable output delay
MHz
ns
ns
ns
ns
FSEROF
TSERCL
TSERCH
TSERCR
TSERCF
10
40
40
10
10
20
20
ns
ns
TSERDOD -20
TSEREOD -20
SEROUT ref SERCLK
SERSEL ref SERCLK
ns
Serialchipselectenabletofirstclock TSERCDC
edge delay
70
ns
Serial last clock edge delay to chip
select disable
TSERCEC
70
Cont…
NOTES
1. The input pair CLK_T, CLK_I may be driven by a low amplitude differential sinewave from an RF Front-end.
Direct DC connection to a GP2010 or GP2015 RF front end is NOT possible, as the maximum DC bias from these
devices is in excess of maximum input bias limit.
2. Jitter is dominated by supply-noise effects. Users must keep on-chip supply noise below 1Vp-p by the use of
low noise outputs and as many supply pins as possible.
13
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
