GP4020
Universal Asynchronous Receive/Transmit
(UART1 and UART2)
The full duplex asynchronous channels of UART1 and
UART2 provide RS232 type interfaces, which support
an XON/XOFF software protocol. The Receive and
Transmit channels are double buffered. The UARTs
may be polled, or may use an interrupt scheme for
module bus transfers. An internal Baud rate generator
in each UART can provide selectable data rates,
derived from on-chip sources for an Rx/Tx pair.
Directly-triggered DMA transfers with each UART are
also possible without the need for CPU intervention.
Watchdog (WDOG)
TheGP4020Watchdogcanbeusedtodetecthardware
or software run-time errors, and reset the system. The
processorisrequiredtoresetthewatchdogperiodically;
failure to do so will result in a chip-wide reset.
Electrical Characteristics
TAMB = -40°C to +85°C, VDD = +3·0V to +3·6V (+3·3V nominal). The input thresholds and output voltage limits for the
logic signal pins are tested and guaranteed by production test. All other parameters are guaranteed by characterisation
and design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise specified.
Use in conjunction with the GP4020 GPS Baseband Processor Design Manual (DM5280).
Value
Min. Typ. Max.
Symbol
Units
Conditions
Characteristic
Operating voltage range
Battery backup voltage
Supply Current
3·0
2·7
3·6
V
V
VBATT
IDD
Full chip
100
mA
Simulated.FireflyBµlLD_CLK=
30MHz, outputs loaded with
50pF, 12 tracking correlator
channels
ILLDI
IPRX
IPLL
4·4
100
0·9
mA
nA
mA
nA
µA
mA
Enabled
Disabled
Enabled
Disabled
Disabled
Enabled - FOUT = 30MHz,
Mult Factor = 3
40MHz low level differential input
Processor clock oscillator
Phase locked loop
< 1 0 0
2·9
1·0
3·4
mA
mA
mA
Enabled - FOUT = 60MHz,
Mult Factor = 6
Enabled - FOUT = 1 20MHz,
Mult Factor = 12
Enabled - FOUT = 240MHz,
Mult Factor = 24
4·5
6·2
IRTC
IFMF1
3·27
0·7
7·75
µA
mA/MHz
Real time clock
Firefly MF1 microcontroller
Firefly MF1 microcontroller
Operating frequency
FBµILD
20
20
31·25
MHz
Bµild_CLK – external memory
at >1 wait state or internal
memory at 0 wait state.
Bµild_CLK – external memory
access at 0 wait state.
FBµILD
27.5
50
MHz
pF
Operating frequency
Output capacitance
Total external load, all outputs
and I/Os
Cont…
12
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